LH28F016SCT-L12 Sharp Electronics, LH28F016SCT-L12 Datasheet - Page 12

• Manufacturer Part Number: LH28F016SCT-L12
• Manufacturer: Sharp Electronics

Specifications of LH28F016SCT-L12

• Cell Type: NOR
• Density: 16Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

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3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacturer
configuration codes for each block, and the master
lock configuration code (see Figure 4). Using the
manufacturer and device codes, the system CPU can
automatically match the device with its proper
algorithms.
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
1FFFFF
01FFFF
00FFFF
Figure 4. Device Identifier Code Memory Map
1F0004
1F0003
1F0002
1F0001
1F0000
010004
010003
010002
010001
010000
000004
000003
000002
000001
000000
The
Block 31 Lock Configuration Code
Master Lock Configuration Code
Block 0 Lock Configuration Code
Block 1 Lock Configuration Code
code,
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Future Implementation
block
(Blocks 2 through 30)
Manufacturer Code
Device Code
device
Reserved for
Reserved for
Reserved for
Reserved for
Reserved for
lock
code,
and
master
Block 31
block
Block 0
Block 1
lock
lock
LHF16C17
3.6 Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V
erasure, byte write, and lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to be
erased. The Byte Write command requires the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require the
command and address within the device (Master
Lock) or block within the device (Block Lock) to be
locked. The Clear Block Lock-Bits command requires
the command and address within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a command
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 16 and 17 illustrate
WE# and CE#-controlled write operations.
4 COMMAND DEFINITIONS
When the V
from the status register, identifier codes, or blocks
are enabled. Placing V
successful block erase, byte write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
PP
=V
PPH1/2/3
PP
, the CUI additionally controls block
voltage ≤ V
PPH1/2/3
PPLK
, Read operations
on V
PP
Rev. 1.1
enables
9