LH28F016SCT-L12 Sharp Electronics, LH28F016SCT-L12 Datasheet
LH28F016SCT-L12
Specifications of LH28F016SCT-L12
Related parts for LH28F016SCT-L12
LH28F016SCT-L12 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F016SCT-L95 Flash Memory (Model No.: LHF16C17) Issue Date: May 12, 1999 ® 16M (2MB × 8) Spec No.: EL104154C Integrated Circuits Group ...
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Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please ...
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INTRODUCTION ................................................... 3 1.1 New Features...................................................... 3 1.2 Product Overview ................................................ 3 2.0 PRINCIPLES OF OPERATION ............................. 7 2.1 Data Protection ................................................... 8 3.0 BUS OPERATION................................................. 8 3.1 Read ................................................................... 8 3.2 Output Disable .................................................... 8 3.3 Standby ...
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... Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F016SCT-L95 offers three levels of protection: absolute protection with V GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F016SCT-L95 is manufactured on SHARP’ ...
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... Both devices share a compatible pinout, status register, and software command similarities enable a clean upgrade from the 28F008SA to LH28F016SCT-L95. When upgrading important to note the following differences: •Because of new feature support, the two devices have different device codes. This allows for software optimization. •V has been lowered from 6 ...
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Individual block locking uses a combination of bits, thirty-two block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. configuration operations ...
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Input Buffer Address Latch Address Counter CE ...
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... Do not float any power pins. With SUPPLY CC to the flash memory are inhibited. Device operations at invalid V Characteristics) produce spurious results and should not be attempted. Block erase, byte write and lock-bit configuration operations with V GND SUPPLY GROUND: Do not float any ground pins. ...
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... PRINCIPLES OF OPERATION The LH28F016SCT-L95 SmartVoltage Flash memory includes an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-Like interface timings ...
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... As with any automated device important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes CPU reset ...
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Read Identifier Codes Operation The read identifier codes operation outputs the manufacturer code, device configuration codes for each block, and the master lock configuration code (see Figure 4). Using the manufacturer and device codes, the system CPU can ...
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Mode Notes Read 1,2,3,8 Output Disable 3 Standby 3 Deep Power-Down 4 Read Identifier Codes 8 Write 3,6,7,8 NOTES: 1. Refer to DC Characteristics. When can for control pins and addresses, and ...
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Bus Cycles Command Req’d. Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Byte Write Block Erase and Byte Write Suspend Block Erase and Byte Write Resume Set Block Lock-Bit Set Master Lock-Bit Clear Block ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and ...
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... The only other valid commands while byte write is suspended are Read Status Register and Byte Write Resume. After Byte Write Resume command is written to the flash memory, the WSM will continue the byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V ...
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Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the ...
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WSMS ESS ECLBS 7 6 SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above Range ...
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Start Write 40H, Address Write Byte Data and Address Read Status Register No 0 Suspend SR.7= Byte Write 1 Full Status Check if Desired Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V ...
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Start Write B0H Read Status Register 0 SR. SR.6= 1 Read or Read Byte Write Byte Write ? Read Array Data Byte Write Loop No Done? Yes Write D0H Block Erase Resumed Figure 7. Block Erase Suspend/Resume ...
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Start Write B0H Read Status Register 0 SR. Byte Write Completed SR.2= 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Byte Write Resumed Read Array Data Figure 8. Byte Write Suspend/Resume ...
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Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error PP 0 ...
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Start Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error Device Protect ...
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... V GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5 Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V The V pin supplies the memory cell current for byte PP writing and block erasing ...
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... When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during or CE# transitions system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. In ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Byte Write and Lock-Bit Configuration ...........0°C to +70°C Temperature under Bias............... -10°C to +80°C Storage Temperature........................ -65°C to +125°C Voltage On Any Pin (except V , ...
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AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times ...
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DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down CCD CC Current I V Read Current CCR Byte Write or ...
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Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout during PPLK PP Normal Operations V V ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Versions Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV ...
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Versions Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# to Output in ...
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Standby V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - RP#(P) V ...
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AC CHARACTERISTICS - WRITE OPERATION Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t Address Setup ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t RP# V Setup to WE# Going High ...
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V ADDRESSES( CE#( OE#( WE#( DATA(D/ RY/BY#( RP#( PPH3,2 PPLK V NOTES power-up and standby Write ...
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ALTERNATIVE CE#-CONTROLLED WRITES Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t Address Setup to CE# ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t RP# V Setup to CE# Going High ...
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V ADDRESSES( WE#( OE#( CE#( DATA(D/ RY/BY#( RP#( PPH3,2 PPLK V NOTES power-up and standby Write ...
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RESET OPERATIONS V OH RY/BY#( RP#( RY/BY#( RP#( 2.7V/3.3V/ RP#( Sym. Parameter RP# Pulse Low Time ...
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BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE Sym. Parameter t WHQV1 Byte Write Time t EHQV1 Block Write Time t WHQV2 Block Erase Time t EHQV2 t WHQV3 Set Lock-Bit Time t EHQV3 t WHQV4 Clear Block ...
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... Architecture S = Regular Block Power Supply Type C = SmartVoltage Technology Operating Temperature blank = 0°C ~ +70° -40°C ~ +85°C Option Order Code 1.35V I/O Levels 1 LH28F016SCT-L95 LH28F016SC-L150 LH28F016SC-L120 LH28F016SC-L100 LH28F016SC-L95 LHF16C17 - ( ) H T Package T = 40-Lead TSOP R = 40-Lead TSOP(Reverse Bend 48-Ball CSP Valid Operational Combinations V =2.7-3.6V V =3.3± ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp EUROPE SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SINGAPORE SHARP Electronics (Singapore) PTE., Ltd. ...