LH28F160BJHE-BTLZD Sharp Electronics, LH28F160BJHE-BTLZD Datasheet - Page 9

• Manufacturer Part Number: LH28F160BJHE-BTLZD
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-BTLZD

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

2 PRINCIPLES OF OPERATION
The LH28F160BJHE-BTLZD flash memory includes an
on-chip WSM to manage block erase, full chip erase, word
write and lock-bit configuration functions. It allows for:
100% TTL-level control inputs, fixed power supplies
during block erase, full chip erase, word write and lock-bit
configuration, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
voltage on V
erase, word write and lock-bit configurations. All
functions associated with altering memory contents−block
erase, full chip erase, word write, lock-bit configuration,
status and identifier codes−are accessed via the CUI and
verified through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, full chip erase,
word write and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification and margining of data.
Addresses and data are internally latched during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block
erase,
configuration can be stored in any block. This code is
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word write suspend allows system software to
suspend a word write to read data from any other flash
memory array location.
full chip erase, word write and lock-bit
CCW
enables successful block erase, full chip
CCW
voltage. High
[A
DFFFF
AFFFF
EFFFF
D7FFF
CFFFF
C7FFF
BFFFF
B7FFF
A7FFF
FFFFF
F7FFF
E7FFF
D8000
D0000
A8000
A0000
9FFFF
8FFFF
7FFFF
6FFFF
5FFFF
4FFFF
3FFFF
2FFFF
1FFFF
0FFFF
19
E8000
E0000
C8000
C0000
B8000
B0000
97FFF
87FFF
77FFF
67FFF
57FFF
47FFF
37FFF
27FFF
17FFF
07FFF
06FFF
05FFF
04FFF
03FFF
02FFF
01FFF
00FFF
F8000
F0000
98000
90000
88000
80000
78000
70000
68000
60000
58000
50000
48000
40000
38000
30000
28000
20000
18000
10000
08000
07000
06000
05000
04000
03000
02000
01000
00000
-A
0
]
Figure 3. Memory Map
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
4K-word Boot Block
4K-word Boot Block
Bottom Boot
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
1
0
Rev. 1.27