LH28F008SCN-V85 Sharp Electronics, LH28F008SCN-V85 Datasheet - Page 4

• Manufacturer Part Number: LH28F008SCN-V85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCN-V85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

PIN DESCRIPTION
SYMBOL
DQ
RY/BY#
A
RP#
WE#
GND
CE#
OE#
V
V
0
NC
0
-A
CC
-DQ
PP
19
7
OUTPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
TYPE
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP# at V
master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP# = V
operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
with V
OUTPUT ENABLE : Gates the device's outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and byte write is inactive, byte write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY : For
erasing array blocks, writing bytes, or configuring lock-bits. With V
contents cannot be altered. Block erase, byte write, and lock-bit configuration with an
invalid V
and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 5 V operation.
Do not float any power pins. With V
are inhibited. Device operations at invalid V
CHARACTERISTICS") produce spurious results and should not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
IH
≤ RP# ≤ V
PP
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results
HH
overrides block lock-bits thereby enabling block erase and byte write
HH
produce spurious results and should not be attempted.
- 4 -
NAME AND FUNCTION
CC
≤ V
LKO
, all write attempts to the flash memory
CC
voltage (see Section 6.2.3 "DC
LH28F008SC-V/SCH-V
HH
enables setting of the
PP
≤ V
PPLK
, memory