LH28F008SCR-V12 Sharp Electronics, LH28F008SCR-V12 Datasheet - Page 11

• Manufacturer Part Number: LH28F008SCR-V12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCR-V12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

NOTES :
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
3. SRD = Data read from status register. See Table 6 for a
4. Following the Read Identifier Codes command, read
5. If the block is locked, RP# must be at V
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Byte Write
Block Erase and
Byte Write Suspend
Block Erase and
Byte Write Resume
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
WD = Data to be written at location WA. Data is latched
ID = Data read from identifier codes.
operations access manufacture, device, block lock, and
master lock codes. See Section 4.2 for read identifier
code data.
block erase or byte write operations. Attempts to issue a
block erase or byte write to a locked block while RP# is
V
IH
.
COMMAND
on the rising edge of WE# or CE# (whichever
goes high first).
description of the status register bits.
BUS CYCLES
REQ
≥ 2
1
2
2
1
1
2
2
2
2
1
Table 3 Command Definitions
’
D.
HH
NOTE
to enable
5, 6
4
5
5
5
7
7
8
Oper
- 11 -
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
(NOTE 1)
FIRST BUS CYCLE
6. Either 40H or 10H is recognized by the WSM as the
7. If the master lock-bit is set, RP# must be at V
8. If the master lock-bit is set, RP# must be at V
9. Commands other than those shown above are reserved
Addr
byte write setup.
block lock-bit. RP# must be at V
lock-bit. If the master lock-bit is not set, a block lock-bit
can be set while RP# is V
block lock-bits. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the master
lock-bit is not set, the Clear Block Lock-Bits command
can be done while RP# is V
by SHARP for future device implementations and should
not be used.
WA
BA
BA
(NOTE 2)
X
X
X
X
X
X
X
X
(NOTE 9)
Data
40H or 10H
D0H
FFH
90H
20H
B0H
60H
60H
70H
50H
60H
(NOTE 3)
Oper
Read
Read
Write
Write
Write
Write
Write
LH28F008SC-V/SCH-V
SECOND BUS CYCLE
IH
(NOTE 1)
.
IH
.
Addr
HH
WA
BA
BA
IA
(NOTE 2)
X
X
X
to set the master
Data
HH
HH
SRD
D0H
D0H
F1H
01H
WD
to set a
to clear
ID
(NOTE 3)