LH28F008SCR-L85 Sharp Electronics, LH28F008SCR-L85 Datasheet - Page 19

• Manufacturer Part Number: LH28F008SCR-L85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCR-L85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

SR.7 = WRITE STATE MACHINE STATUS
SR.6 = ERASE SUSPEND STATUS
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS
SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS
SR.3 = V
SR.2 = BYTE WRITE SUSPEND STATUS
SR.1 = DEVICE PROTECT STATUS
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
1 = Error in Byte Write or Set Master/Block Lock-Bit
0 = Successful Byte Write or Set Master/Block
1 = V
0 = V
1 = Byte Write Suspended
0 = Byte Write in Progress/Completed
1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock
0 = Unlock
7
Lock-Bit
Detected, Operation Abort
PP
PP
PP
STATUS
Low Detect, Operation Abort
OK
ESS
6
ECLBS
5
Table 7. Status Register Definition
BWSLBS
4
LHF08CTF
NOTES:
Check RY/BY# or SR.7 to determine block erase, byte
write, or lock-bit configuration completion.
SR.6-0 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase or
lock-bit configuration attempt, an improper command
sequence was entered.
SR.3 does not provide a continuous indication of V
level. The WSM interrogates and indicates the V
only after Block Erase, Byte Write, Set Block/Master
Lock-Bit, or Clear Block Lock-Bits command sequences.
SR.3 is not guaranteed to reports accurate feedback
only when V
SR.1 does not provide a continuous indication of master
and block lock-bit values. The WSM interrogates the
master lock-bit, block lock-bit, and RP# only after Block
Erase, Byte Write, or Lock-Bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set, master
lock-bit is set, and/or RP# is not V
lock and master lock configuration codes after writing
the Read Identifier Codes command indicates master
and block lock-bit status.
SR.0 is reserved for future use and should be masked
out when polling the status register.
VPPS
3
PP
≠V
PPH1/2/3
BWSS
2
.
DPS
HH
1
. Reading the block
PP
Rev. 1.3
R
0
PP
level
16