LH28F008SCR-L85 Sharp Electronics, LH28F008SCR-L85 Datasheet - Page 17

• Manufacturer Part Number: LH28F008SCR-L85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCR-L85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

4.8 Byte Write Suspend Command
The Byte Write Suspend command allows byte write
interruption to read data in other flash memory
locations. Once the byte write process starts, writing
the Byte Write Suspend command requests that the
WSM suspend the byte write sequence at a
predetermined point in the algorithm. The device
continues to output status register data when read
after the Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the byte write operation has been
suspended (both will be set to "1"). RY/BY# will also
transition to V
byte write suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
byte write is suspended are Read Status Register
and Byte Write Resume. After Byte Write Resume
command is written to the flash memory, the WSM
will continue the byte write process. Status register
bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to V
Resume
automatically outputs status register data when read
(see Figure 8). V
same V
suspend mode. RP# must also remain at V
(the same RP# level used for byte write).
4.9 Set Block and Master Lock-Bit
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program and
erase operations while the master lock-bit gates
block-lock bit modification. With the master lock-bit
not set, individual block lock-bits can be set using the
Set Block Lock-Bit command. The Set Master
Lock-Bit command, in conjunction with RP#=V
sets the master lock-bit. After the master lock-bit is
set, subsequent setting of block lock-bits requires
both the Set Block Lock-Bit command and V
Commands
PP
level used for byte write) while in byte write
command
OH
. Specification t
PP
must remain at V
is
OL
. After the Byte Write
written,
WHRH1
the
PPH1/2/3
defines the
IH
or V
device
HH
(the
HH
LHF08CTF
HH
on
,
the RP# pin. See Table 6 for a summary of hardware
and software write protection options.
Set block lock-bit and master lock-bit are executed by
a two-cycle command sequence. The set block or
master lock-bit setup along with appropriate block or
device address is written followed by either the set
block lock-bit confirm (and an address within the
block to be locked) or the set master lock-bit confirm
(and any device address). The WSM then controls
the set lock-bit algorithm. After the sequence is
written, the device automatically outputs status
register data when read (see Figure 9). The CPU can
detect the completion of the set lock-bit event by
analyzing the RY/BY# pin output or status register bit
SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations occur
only when V
absence of this high voltage, lock-bit contents are
protected against alteration.
A successful set block lock-bit operation requires that
the master lock-bit be cleared or, if the master
lock-bit is set, that RP#=V
the master lock-bit set and RP#=V
will be set to "1" and the operation will fail. Set block
lock-bit operations while V
spurious results and should not be attempted. A
successful set master lock-bit operation requires that
RP#=V
SR.4 will be set to "1" and the operation will fail. Set
master
produce
attempted.
HH
lock-bit
. If it is attempted with RP#=V
spurious
CC
=V
CC2/3/4
operations
results
and V
HH
. If it is attempted with
IH
and
<RP#<V
with
PP
IH
=V
should
, SR.1 and SR.4
PPH1/2/3
V
IH
HH
IH
<RP#<V
, SR.1 and
Rev. 1.3
produce
not
. In the
14
HH
be