LH28F008SCT-V12 Sharp Electronics, LH28F008SCT-V12 Datasheet - Page 22

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LH28F008SCT-V12

Manufacturer Part Number
LH28F008SCT-V12
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LH28F008SCT-V12

Cell Type
NOR
Density
8Mb
Access Time (max)
120ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
20b
Operating Supply Voltage (typ)
5V
Operating Temp Range
0C to 70C
Package Type
TSOP-I
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8b
Number Of Words
1M
Supply Current
50mA
Mounting
Surface Mount
Pin Count
40
Lead Free Status / Rohs Status
Not Compliant
FULL STATUS CHECK PROCEDURE
Clear Block Lock-Bits
Read Status Register
Clear Block Lock-Bits
Data (See Above)
Check if Desired
Status Register
Successful
Full Status
Write D0H
Write 60H
Complete
SR.4, 5 =
SR.7 =
SR.3 =
SR.1 =
SR.5 =
Read
Start
0
0
0
0
1
0
1
1
1
1
Clear Block Lock-Bits
Command Sequence
Device Protect Error
V
PP
Fig. 8 Clear Block Lock-Bits Flowchart
Range Error
Error
Error
- 22 -
OPERATION
OPERATION COMMAND
Write
Write
Read
Standby
Standby
Standby
Standby
Standby
Write FFH after the last clear block lock-bits operation to place
device in read array mode.
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command.
If error is detected, clear the status register before attempting
retry or other error recovery.
BUS
BUS
COMMAND
Clear Block
Clear Block
Lock-Bits
Lock-Bits
Confirm
Setup
Check SR.3
1 = V
Check SR.1
1 = Device Protect Detect
RP# = V
Check SR.4, 5
Both 1 = Command Sequence Error
Check SR.5
1 = Clear Block Lock-Bits Error
Data = 60H
Addr = X
Data = D0H
Addr = X
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
PP
Error Detect
IH
, Master Lock-Bit is Set
COMMENTS
COMMENTS
LH28F008SC-V/SCH-V

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