LH28F008SCT-V12 Sharp Electronics, LH28F008SCT-V12 Datasheet - Page 16

• Manufacturer Part Number: LH28F008SCT-V12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCT-V12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

SR.7 = WRITE STATE MACHINE STATUS (WSMS)
SR.6 = ERASE SUSPEND STATUS (ESS)
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS (ECLBS)
SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS (BWSLBS)
SR.3 = V
SR.2 = BYTE WRITE SUSPEND STATUS (BWSS)
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
OPERATION
Block Erase
or Byte Write
Set Block
Lock-Bit
Set Master
Lock-Bit
Clear Block
Lock-Bits
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erase or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
1 = Error in Byte Write or Set Master/Block Lock-Bit
0 = Successful Byte Write or Set Master/Block Lock-Bit
1 = V
0 = V
1 = Byte Write Suspended
0 = Byte Write in Progress/Completed
1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock
0 = Unlock
7
Detected, Operation Abort
PP
PP
PP
STATUS (VPPS)
Low Detect, Operation Abort
OK
LOCK-BIT LOCK-BIT
MASTER
ESS
X
X
0
1
0
1
6
BLOCK
0
1
X
X
X
X
X
ECLBS
5
Table 5 Write Protection Alternatives
V
V
V
Table 6 Status Register Definition
IH
IH
IH
RP#
V
V
V
V
V
V
V
V
or V
or V
or V
HH
HH
HH
HH
IH
IH
IH
IH
BWSLBS
HH
HH
HH
4
Block Erase and Byte Write Enabled
Block is Locked. Block Erase and Byte Write Disabled
Block Lock-Bit Override. Block Erase and Byte Write Enabled
Set Block Lock-Bit Enabled
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
Master Lock-Bit Override. Set Block Lock-Bit Enabled
Set Master Lock-Bit Disabled
Set Master Lock-Bit Enabled
Clear Block Lock-Bits Enabled
Master Lock-Bit is Set. Clear Block Lock-Bits Disabled
Master Lock-Bit Override. Clear Block Lock-Bits Enabled
- 16 -
NOTES :
Check RY/BY# or SR.7 to determine block erase, byte write,
or lock-bit configuration completion.
SR.6-0 are invalid while SR.7 = "0".
If both SR.5 and SR.4 are "1"s after a block erase or lock-bit
configuration attempt, an improper command sequence was
entered.
SR.3 does not provide a continuous indication of V
The WSM interrogates and indicates the V
Block Erase, Byte Write, Set Block/Master Lock-Bit, or Clear
Block Lock-Bits command sequences.
SR.3 is not guaranteed to reports accurate feedback only
when V
SR.1 does not provide a continuous indication of master and
block lock-bit values. The WSM interrogates the master lock-
bit, block lock-bit, and RP# only after Block Erase, Byte Write,
or Lock-Bit configuration command sequences. It informs the
system, depending on the attempted operation, if the block
lock-bit is set, master lock-bit is set, and/or RP# is not V
Reading the block lock and master lock configuration codes
after writing the Read Identifier Codes command indicates
master and block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
VPPS
3
PP
V
PPH1/2
BWSS
.
EFFECT
2
LH28F008SC-V/SCH-V
DPS
1
PP
level only after
PP
R
0
level.
HH
.