LH28F800SGN-L10 Sharp Electronics, LH28F800SGN-L10 Datasheet - Page 6
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LH28F800SGN-L10
Manufacturer Part Number
LH28F800SGN-L10
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F800SGN-L10.pdf
(42 pages)
Specifications of LH28F800SGN-L10
Cell Type
NOR
Density
8Mb
Interface Type
Parallel
Boot Type
Not Required
Address Bus
19b
Operating Supply Voltage (typ)
3.3/5V
Operating Temp Range
0C to 70C
Package Type
SOP
Program/erase Volt (typ)
2.7/3.3/5/12V
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7/4.5V
Operating Supply Voltage (max)
3.6/5.5V
Word Size
16b
Number Of Words
512K
Supply Current
65mA
Mounting
Surface Mount
Pin Count
44
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LH28F800SGN-L10
Manufacturer:
SHARP
Quantity:
9 020
The selected block can be locked or unlocked
individually by the combination of sixteen block lock
bits and the RP#. Block erase or word write must
not be carried out by setting block lock bits and
RP# to V
and word write to locked blocks is prohibited by
setting permanent lock bit.
The status register or RY/BY# indicates when the
WSM’s block erase, word write, or lock-bit
configuration operation is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase, word write, or
lock-bit configuration.
RY/BY#-high indicates that the WSM is ready for a
new command, block erase is suspended (and
word write is inactive), word write is suspended, or
the device is in deep power-down mode.
The access time is 70 ns (t
voltage range of 4.75 to 5.25 V over the
temperature range (0 to +70˚C). At 4.5 to 5.5 V
V
V
(3.0 to 3.6 V) and 100 ns or 120 ns (2.7 to 3.0 V).
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
5 V V
CC
CC
, the access time is 80 ns or 100 ns. At lower
voltage, the access time is 85 ns or 100 ns
CC
and 3 mA at 2.7 to 3.6 V V
IH
. Even if RP# is set to V
AVQV
CCR
) at the V
current is 1 mA at
HH
CC
, block erase
.
CC
supply
- 6 -
When CE# and RP# pins are at V
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
Fig. 1 Memory Map
LH28F800SG-L (FOR SOP)
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
CC
15
14
13
12
11
10
, the I
9
8
7
6
5
4
3
2
1
0
PHQV
PHEL
) is
CC
)