LH28F800BJHE-PTTLT6 Sharp Electronics, LH28F800BJHE-PTTLT6 Datasheet - Page 43

LH28F800BJHE-PTTLT6

Manufacturer Part Number
LH28F800BJHE-PTTLT6
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LH28F800BJHE-PTTLT6

Cell Type
NOR
Density
8Mb
Access Time (max)
90ns
Interface Type
Parallel
Boot Type
Top
Address Bus
20/19Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Compliant
6.2.7 Reset Operations
NOTES:
1. If RP# is asserted while a block erase, full chip erase, word/byte write or lock-bit configuration operation is not executing,
2. A reset time, t
3. When the device power-up, holding RP# low minimum 100ns is required after V
t
t
t
PLPH
PLRZ
2VPH
Sym.
the reset will complete within 100ns.
valid. Refer to AC Characteristics - Read-Only Operations for t
has been in stable there.
RP# Pulse Low Time
RP# Low to Reset during Block Erase, Full Chip Erase,
Word/Byte Write or Lock-Bit Configuration
V
CC
2.7V to RP# High
PHQV
RY/BY#(R)
RY/BY#(R)
RP#(P)
RP#(P)
RP#(P)
(SR.7)
(SR.7)
V
CC
, is required from the later of RY/BY#(SR.7) going High Z("1") or RP# going high until outputs are
High Z
High Z
("0")
("0")
2.7V
("1")
V
("1")
V
V
V
V
V
V
V
V
OL
OL
IH
IH
IH
IL
IL
IL
IL
(B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration
Parameter
Figure 20. AC Waveform for Reset Operation
t
t
PLPH
PLPH
Reset AC Specifications
(A)Reset During Read Array Mode
t
2VPH
t
PLRZ
(C)RP# rising Timing
PHQV
.
Notes
1,2
2,3
2
CC
has been in predefined range and also
Min.
100
100
Max.
30
Rev. 1.27
Unit
ns
µs
ns

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