LH28F800BGHE-BL85 Sharp Electronics, LH28F800BGHE-BL85 Datasheet - Page 4
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LH28F800BGHE-BL85
Manufacturer Part Number
LH28F800BGHE-BL85
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F800BGHE-BL85.pdf
(43 pages)
Specifications of LH28F800BGHE-BL85
Cell Type
NOR
Density
8Mb
Interface Type
Parallel
Boot Type
Bottom
Address Bus
19b
Operating Supply Voltage (typ)
3.3/5V
Operating Temp Range
-40C to 85C
Package Type
TSOP-I
Program/erase Volt (typ)
2.7/3.3/5/12V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7/4.5V
Operating Supply Voltage (max)
3.6/5.5V
Word Size
16b
Number Of Words
512K
Supply Current
65mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant
PIN DESCRIPTION
DQ
SYMBOL
RY/BY#
A
RP#
WE#
WP#
GND
CE#
OE#
V
0
V
0
NC
-DQ
-A
CC
PP
18
15
OUTPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY
INPUT/
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
TYPE
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins float
to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE : Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode. With RP# = V
write can operate to all blocks without WP# state. Block erase or word write with V
RP# < V
OUTPUT ENABLE : Gates the device’s outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
WRITE PROTECT : Master control for boot blocks locking. When V
blocks cannot be erased and programmed.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase or word write). RY/BY#-high indicates that
the WSM is ready for new commands, block erase is suspended, and word write is
inactive, word write is suspended, or the device is in deep power-down mode. RY/BY#
is always active and does not float when the chip is deselected or data outputs are
disabled.
BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or
writing words. With V
word write with an invalid V
spurious results and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V, 3.3 V or
5 V operation. To switch from one voltage to another, ramp V
ramp V
attempts to the flash memory are inhibited. Device operations at invalid V
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
CC
HH
to the new voltage. Do not float any power pins. With V
produce spurious results and should not be attempted.
PP
≤ V
- 4 -
PP
PPLK
(see Section 6.2.3 "DC CHARACTERISTICS") produce
NAME AND FUNCTION
, memory contents cannot be altered. Block erase and
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
CC
HH
down to GND and then
, block erase or word
CC
≤ V
IL
, locked boot
LKO
CC
, all write
voltage
IH
<