LH28F800BVE-BV85 Sharp Electronics, LH28F800BVE-BV85 Datasheet - Page 6

• Manufacturer Part Number: LH28F800BVE-BV85
• Manufacturer: Sharp Electronics

Specifications of LH28F800BVE-BV85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

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1 INTRODUCTION
This datasheet contains LH28F800BVE-BV85
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
1.1 Features
Key enhancements of LH28F800BVE-BV85 Smart5 Flash
memory are:
Please note following important differences:
1.2 Product Overview
The LH28F800BVE-BV85 is a high-performance 8M-bit
Smart5 Flash memory organized as 1M-byte of 8 bits or
512K-word of 16 bits. The 1M-byte/512K-word of data is
arranged in two 8K-byte/4K-word boot blocks, six 8K-
byte/4K-word parameter blocks and fifteen 64K-byte/32K-
word main blocks which are individually erasable in-
system. The memory map is shown in Figure 3.
Smart5 technology provides a choice of V
combinations, as shown in Table 1, to meet system
performance and power expectations. V
•Smart5 Technology
•Enhanced Suspend Capabilities
•Boot Block Architecture
•V
•To take advantage of Smart5 technology, allow V
block erase and word/byte write operations. The V
voltage transitions to GND is recommended for
designs that switch V
and V
PPLK
PP
has been lowered to 1.5V to support 4.5V-5.5V
connection to 4.5V-5.5V.
PP
off during read operation.
PP
at 4.5V-5.5V
CC
and V
CC
LHF80V35
PP
PP
eliminates the need for a separate 12V converter, while
V
performance. In addition to flexible erase and program
voltages, the dedicated V
protection when V
Internal V
configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase and word/byte write
operations.
A block erase operation erases one of the device’s 32K-
word blocks typically within 0.39s (5V V
4K-word blocks typically within 0.25s (5V V
V
independently erased 100,000 times. Block erase suspend
mode allows system software to suspend block erase to
read or write data from any other block.
Writing memory data is performed in
increments of the device’s 32K-word blocks typically
within 8.4µs (5V V
typically within 17µs (5V V
write suspend mode enables the system to read data or
execute code from any other flash memory array location.
Table 1. V
PP
PP
=12V maximizes block erase and word/byte write
) independent of other blocks. Each block can be
V
4.5V-5.5V
CC
CC
Voltage
CC
and V
and V
PP
Smart5 Technology
≤V
PP
PP
CC
PPLK
Voltage Combinations Offered by
detection Circuitry automatically
, 12V V
PP
.
4.5V-5.5V, 11.4V-12.6V
CC
pin gives complete data
, 12V V
V
PP
PP
), 4K-word blocks
Voltage
PP
CC
). Word/byte
, 12V V
word/byte
CC
Rev. 1.2
, 12V
PP
3
),