LH28F800BVE-BV85 Sharp Electronics, LH28F800BVE-BV85 Datasheet
LH28F800BVE-BV85
Specifications of LH28F800BVE-BV85
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LH28F800BVE-BV85 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F800BVE-BV85 Flash Memory 8M (1MB × 512KB × 16) (Model No.: LHF80V35) Issue Date: September 28, 1999 ® Spec No.: EL109091B Integrated Circuits Group ...
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Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please ...
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INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 2 PRINCIPLES OF OPERATION........................................ 7 2.1 Data Protection............................................................. 8 3 BUS OPERATION ............................................................ 8 3.1 Read.............................................................................. 8 3.2 Output Disable.............................................................. 8 3.3 Standby......................................................................... 8 3.4 Deep Power-Down ....................................................... ...
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... Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800BVE-BV85 offers two levels of protection: absolute protection with V at GND, selective hardware boot block locking ...
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... Smart5 technology, allow V and V connection to 4.5V-5.5V. PP 1.2 Product Overview The LH28F800BVE-BV85 is a high-performance 8M-bit Smart5 Flash memory organized as 1M-byte of 8 bits or 512K-word of 16 bits. The 1M-byte/512K-word of data is arranged in two 8K-byte/4K-word boot blocks, six 8K- byte/4K-word parameter blocks and fifteen 64K-byte/32K- word main blocks which are individually erasable in- system ...
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The boot blocks can be locked for the WP# pin. Block erase or word/byte write for boot block must not be carried out by WP# to Low and RP The status register indicates when the ...
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Input Decoder Buffer Address Latch Decoder Address Counter ...
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... V not be attempted. DEVICE POWER SUPPLY: Do not float any power pins. With V V SUPPLY the flash memory are inhibited. Device operations at invalid V CC produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins. ...
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... PRINCIPLES OF OPERATION The LH28F800BVE-BV85 Smart5 Flash memory includes an on-chip WSM to manage block erase and word/byte write functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure and word/byte write, and minimal processor overhead with RAM-like interface timings. ...
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... Refer to Table 6 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes ...
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Read Identifier Codes Operation The read identifier codes operation manufacturer code and device code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms ...
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Mode Notes Read 8 Output Disable Standby 10 Deep Power-Down 4,10 Read Identifier Codes 8 Write 6,7,8 Mode Notes V Read 8 V Output Disable V Standby 10 Deep Power-Down 4,10 V Read Identifier Codes 8,9 V Write 6,7,8 ...
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Bus Cycles Command Req’d. Read Array/Reset 1 ≥2 Read Identifier Codes Read Status Register 2 Clear Status Register 1 Block Erase 2 Word/Byte Write 2 Block Erase and Word/Byte 1 Write Suspend Block Erase and Word/Byte 1 Write Resume ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads ...
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... HH suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to V the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 7) ...
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... V The V PP complete write protection of all blocks in the flash device. 4.10.2 WP#=V The lockable blocks are locked when WP#=V program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two boot blocks are lockable ...
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WSMS ESS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= ...
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Start Write 40H or 10H, Address Write Word/Byte Data and Address Read Status Register No 0 Suspend SR.7= Word/Byte Write Yes 1 Full Status Check if Desired Word/Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) ...
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Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Read or Read Word/Byte Write Word/Byte Write? Read Array Data Word/Byte Write Loop No Done? Yes Write D0H Block Erase Resumed Read Array Data ...
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Start Write B0H Read Status Register 0 SR. Word/Byte Write SR.2= Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Word/Byte Write Read Array Data Resumed Figure 8. Word/Byte Write Suspend/Resume ...
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... PC board trace inductance. 5.4 V Trace on Printed Circuit Boards PP Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V Power supply trace. The V PP supplies the memory cell current for word/byte writing and block erasing ...
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... When designing portable systems, designers must consider clear IL battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. . LKO ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase and Word/Byte Write.................................0°C to +70°C Temperature under Bias ...................... -10°C to +80°C Storage Temperature ................................ -65°C to +125°C Voltage On Any Pin (except ...
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AC INPUT/OUTPUT TEST CONDITIONS 3.0 INPUT 0.0 AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times ...
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DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down Current CCD Read Current CCR Word/Byte Write Current ...
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Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout Voltage during Normal PPLK PP Operations V ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z ...
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AC CHARACTERISTICS - WRITE OPERATIONS Sym. t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t RP# V Setup to ...
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V ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#(F) V High Z RY/BY#( WP#( RP#( PPH2 (V) PP PPLK V NOTES: 1. ...
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ALTERNATIVE CE#-CONTROLLED WRITES Sym. t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t RP# V Setup to CE# Going ...
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V ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#(F) V High Z RY/BY#( WP#( RP#( PPH2 (V) PP PPLK V NOTES: 1. ...
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RESET OPERATIONS High Z RY/BY#( RP#( High Z RY/BY#( RP#( RP#( Sym. RP# Pulse Low Time t ...
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BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE Sym. Parameter t Word/Byte Write Time 32K word Block WHQV1 t 4K word Block EHQV1 Block Write Time 32K word Block 4K word Block t Block Erase Time 32K word Block WHQV2 ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp EUROPE SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SINGAPORE SHARP Electronics (Singapore) PTE., Ltd. ...