LH28F400BVE-TL85 Sharp Electronics, LH28F400BVE-TL85 Datasheet - Page 6

• Manufacturer Part Number: LH28F400BVE-TL85
• Manufacturer: Sharp Electronics

Specifications of LH28F400BVE-TL85

• Cell Type: NOR
• Density: 4Mb
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7/3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

The boot blocks can be locked for the WP# pin. Block
erase or word/byte write for boot block must not be carried
out by WP# to Low and RP# to V
The status register indicates when the WSM’s block erase
or word/byte write operation is finished.
The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RY/BY# minimizes both CPU overhead and
system power consumption. When low, RY/BY# indicates
that the WSM is performing a block erase or word/byte
write. RY/BY#-high indicates that the WSM is ready for a
new command, block erase is suspended (and word/byte
write is inactive), word/byte write is suspended, or the
device is in deep power-down mode.
The access time is 85ns (t
temperature range (0°C to +70°C) and V
range of 4.75V-5.25V. At lower V
AVQV
IH
) over the commercial
CC
.
voltages, the access
CC
supply voltage
times are 90ns (4.5V-5.5V), 100ns (3.0V-3.6V) and 120ns
(2.7V-3.6V).
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical I
current is 1mA at 5V V
When CE# and RP# pins are at V
standby mode is enabled. When the RP# pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection during
reset. A reset time (t
high until outputs are valid. Likewise, the device has a
wake time (t
are recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 48-lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in Figure
2.
PHEL
) from RP#-high until writes to the CUI
PHQV
CC
) is required from RP# switching
.
CC
, the I
CC
Rev. 1.02
CMOS
CCR