LH28F400BVE-TL85 Sharp Electronics, LH28F400BVE-TL85 Datasheet
LH28F400BVE-TL85
Specifications of LH28F400BVE-TL85
Available stocks
Related parts for LH28F400BVE-TL85
LH28F400BVE-TL85 Summary of contents
Page 1
... Flash Memory LH28F400BVE-TL85 Date Sep. 21. 1999 ...
Page 2
Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
Page 3
INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 2 PRINCIPLES OF OPERATION........................................ 7 2.1 Data Protection............................................................. 7 3 BUS OPERATION ............................................................ 8 3.1 Read.............................................................................. 8 3.2 Output Disable.............................................................. 8 3.3 Standby......................................................................... 8 3.4 Deep Power-Down ....................................................... 8 ...
Page 4
... Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F400BVE-TL85 offers two levels of protection: absolute protection with V at GND, selective hardware boot block locking ...
Page 5
... V connection to 2.7V, 3. 1.2 Product Overview The LH28F400BVE-TL85 is a high-performance 4M-bit SmartVoltage Flash memory organized as 512K-byte of 8 bits or 256K-word of 16 bits. The 512K-byte/256K-word of data is arranged in two 8K-byte/4K-word boot blocks, six 8K-byte/4K-word parameter blocks and seven 64K- byte/32K-word main blocks which are individually erasable in-system ...
Page 6
The boot blocks can be locked for the WP# pin. Block erase or word/byte write for boot block must not be carried out by WP# to Low and RP The status register indicates when the WSM’s ...
Page 7
Output Buffer Y Input Decoder Buffer X Address Latch Decoder Address Counter Figure 1. Block Diagram ...
Page 8
... Block erase and PP PPLK (see DC Characteristics) produce spurious results and should PP down to GND and then ramp LKO voltage (see DC Characteristics) produce <RP#<V produce spurious locked boot blocks cannot IL , 0-7 input buffer all write attempts to the flash Rev. 1.02 ...
Page 9
... PRINCIPLES OF OPERATION The LH28F400BVE-TL85 SmartVoltage Flash memory includes an on-chip WSM to manage block erase and word/byte write functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure and word/byte write, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power- down mode (see Bus Operations), the device defaults to read array mode ...
Page 10
... BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes or status register independent of the either The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or Read Status Register) to the CUI ...
Page 11
Read Identifier Codes Operation The read identifier codes operation manufacturer code and device code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms ...
Page 12
Mode Notes Read 8 Output Disable Standby 10 Deep Power-Down 4,10 Read Identifier Codes 8 Write 6,7,8 Mode Notes Read 8 Output Disable Standby 10 Deep Power-Down 4,10 Read Identifier Codes 8,9 Write 6,7,8 NOTES: 1. Refer to DC Characteristics. ...
Page 13
Bus Cycles Command Req’d. Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Word/Byte Write Block Erase and Word/Byte Write Suspend Block Erase and Word/Byte Write Resume NOTES: 1. BUS operations are defined in Table 3.1 ...
Page 14
Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
Page 15
... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return RP#=V ...
Page 16
... V The V PP complete write protection of all blocks in the flash device. 4.10.2 WP#=V The lockable blocks are locked when WP#=V program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two boot blocks are lockable ...
Page 17
WSMS ESS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE STATUS ...
Page 18
Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 ...
Page 19
Start Write 40H or 10H, Address Write Word/Byte Data and Address Read Status Register Suspend Word/Byte No 0 Suspend SR.7= Word/Byte Write Yes 1 Full Status Check if Desired Word/Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See ...
Page 20
Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Read or Read Word/Byte Write Word/Byte Write? Read Array Data Word/Byte Write Loop No Done? Yes Write D0H Write FFH Read Array Data Block Erase ...
Page 21
Start Write B0H Read Status Register 0 SR. Word/Byte Write SR.2= Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Word/Byte Write Read Array Data Resumed Figure 8. Word/Byte Write Suspend/Resume Flowchart ...
Page 22
... V Trace on Printed Circuit Boards PP Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V supplies the memory cell current for word/byte writing and block erasing. Use similar trace widths and layout ...
Page 23
... When designing portable systems, designers must consider clear IL battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. . LKO ...
Page 24
ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase and Word/Byte Write.................................0°C to +70°C Temperature under Bias ...................... -10°C to +80°C Storage Temperature ................................ -65°C to +125°C Voltage On Any Pin (except ...
Page 25
AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% ...
Page 26
DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down CCD CC Current I V Read Current CCR Word/Byte Write CCW CC ...
Page 27
Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout Voltage during PPLK PP Normal Operations V V ...
Page 28
AC CHARACTERISTICS - READ-ONLY OPERATIONS Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# ...
Page 29
Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# to Output in Low Z ELQX ...
Page 30
Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV V ...
Page 31
Standby Address Selection V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z DATA(D/Q) ...
Page 32
AC CHARACTERISTICS - WRITE OPERATIONS Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t RP#V Setup to WE# ...
Page 33
Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t RP# V Setup to WE# Going High PHHWH HH t ...
Page 34
Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t RP# V Setup to WE# Going High PHHWH HH t ...
Page 35
V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ BYTE#( RY/BY#( ...
Page 36
ALTERNATIVE CE#-CONTROLLED WRITES Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t RP#V Setup to CE# Going High ...
Page 37
Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t RP# V Setup to CE# Going High PHHEH HH t ...
Page 38
Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t RP# V Setup to CE# Going High PHHEH HH t ...
Page 39
V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ BYTE#( RY/BY#( ...
Page 40
RESET OPERATIONS V OH RY/BY#( RP#( RY/BY#( RP#( 2.7V/3.3V/ RP#( Sym. Parameter RP# Pulse Low Time t ...
Page 41
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE Sym. Parameter t Word/Byte 32K word WHQV1 t Write Time Block EHQV1 4K word Block Block Write 32K word Time Block 4K word Block t Block Erase 32K word WHQV2 t Time Block ...
Page 42
Sym. Parameter t Word/Byte Write Time 32K word Block WHQV1 t 4K word Block EHQV1 Block Write Time 32K word Block 4K word Block t Block Erase Time 32K word Block WHQV2 t 4K word Block EHQV2 t Word/Byte Write ...
Page 43
... Such noises, when induced onto WE# signal or power supply, may be interpreted as false commands, causing undesired memory updating. To protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) Protecting data in specific block By setting a WP# to low, only the boot block can be protected against overwriting ...
Page 44
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
Page 45
A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
Page 46
A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
Page 47
... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...