AT49LV8192A-70TC Atmel, AT49LV8192A-70TC Datasheet - Page 6

• Manufacturer Part Number: AT49LV8192A-70TC
• Manufacturer: Atmel

Specifications of AT49LV8192A-70TC

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 3 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 25mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

TOGGLE BIT: In addition to Data Polling, the AT49BV/LV008A(T)/8192A(T) provides
another method for determining the end of a program or erase cycle. During a program
or erase operation, successive attempts to read data from the device will result in I/O6
toggling between one and zero. Once the program cycle has completed, I/O6 will stop
toggling and valid data will be read. Examining the toggle bit may begin at any time dur-
ing a program cycle.
READY/BUSY: For the AT49BV/LV008A(T), pin 12 is an open-drain Ready/Busy output
pin that provides another method of detecting the end of a program or erase operation.
RDY/BUSY is actively pulled low during the internal program and erase cycles and it is
released at the completion of the cycle. The open-drain connection allows for OR-tying
of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro-
grams to the AT49BV/LV008A(T)/8192A(T) in the following ways: (a) V
sense: if V
CC
CC
is below 1.8V (typical), the program function is inhibited. (b) V
power on delay: once
CC
V
has reached the V
sense level, the device will automatically time-out 10 ms (typi-
CC
CC
cal) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE
high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs
and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely
affecting the operation of the device. The I/O lines can only be driven from 0 to V
+
CC
0.6V.
AT49BV/LV008A(T) ALTERNATE PIN DEFINITION: Two AT49BV/LV008A(T) BGA pin
definitions are shown. The standard pin definition allows use of the JEDEC standard
programming algorithm. If the alternate pin definition is used, the programming algo-
rithm must be modified as shown in the Command Definition for Alternate Pin Definition
table on page 8.
AT49BV/LV008A(T)/8192A(T)
6
1049K–FLASH–11/02