AT49LV8192A-70TC Atmel, AT49LV8192A-70TC Datasheet

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AT49LV8192A-70TC

Manufacturer Part Number
AT49LV8192A-70TC
Description
Manufacturer
Atmel
Datasheet

Specifications of AT49LV8192A-70TC

Cell Type
NOR
Density
8Mb
Access Time (max)
70ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
20/19Bit
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
TSOP-I
Program/erase Volt (typ)
3 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
25mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant

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Features
Description
The AT49BV/LV008A(T) and AT49BV/LV8192A(T) are 3-volt, 8-megabit Flash memo-
ries organized as 1,048,576 words of 8 bits each or 512K words of 16 bits each.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer
access times to 70 ns with power dissipation of just 67 mW at 2.7V read. When dese-
lected, the CMOS standby current is less than 50 µA.
Pin Configurations
Pin Name
A0 - A18
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time – 70 ns
Internal Erase/Program Control
Sector Architecture
Fast Sector Erase Time – 10 seconds
Byte-by-byte or Word-by-word Programming – 30 µs Typical
Hardware Data Protection
Data Polling for End of Program Detection
Low Power Dissipation
Typical 10,000 Write Cycles
– One 8K Word (16K Bytes) Boot Block with Programming Lockout
– Two 4K Word (8K Bytes) Parameter Blocks
– One 496K Word (992K Bytes) Main Memory Array Block
– 25 mA Active Current
– 50 µA CMOS Standby Current
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy Output
VPP can be left unconnected or connected to VCC, GND, 5V or
12V. The input has no effect on the operation of the device.
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
8-megabit
(1M x 8/
512K x 16)
Flash Memory
AT49BV008A
AT49BV008AT
AT49LV008A
AT49LV008AT
AT49BV8192A
AT49BV8192AT
AT49LV8192A
AT49LV8192AT
Not Recommended
for New Design
Contact Atmel to discuss
the latest design in trends
and options
Rev. 1049K–FLASH–11/02
1

Related parts for AT49LV8192A-70TC

AT49LV8192A-70TC Summary of contents

Page 1

... A-1 (LSB Address Input, Byte Mode) BYTE Selects Byte or Word Mode NC No Connect 8-megabit ( 512K x 16) Flash Memory AT49BV008A AT49BV008AT AT49LV008A AT49LV008AT AT49BV8192A AT49BV8192AT AT49LV8192A AT49LV8192AT Not Recommended for New Design Contact Atmel to discuss the latest design in trends and options Rev. 1049K–FLASH–11/02 1 ...

Page 2

... A15 A10 WE RST A16 A13 A17 NC I/O5 NC I/O0 GND E NC A11 I/ GND I/O7 NC I/O4 A17 GND NC A-1 A10 I/O7 I/O6 I/O5 I/O4 VCC VCC NC I/O3 I/O2 I/O1 I/O0 OE GND A19 A18 I/ I/O3 NC I/O0 GND VCC NC I/O1 OE 1049K–FLASH–11/02 ...

Page 3

... WE CE RESET ADDRESS INPUTS 1049K–FLASH–11/02 AT49BV/LV008A(T)/8192A(T) changed when input levels of 5.5 volts or less are used. The boot sector is designed to contain user secure code. For the AT49BV/LV8192A(T), the BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at a logic “1” or left open, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic “ ...

Page 4

... BYTE/WORD PROGRAMMING: Once a memory block is erased programmed (to a logic “0” byte-by-byte or word-by-word basis. Programming is accomplished via 1049K–FLASH–11/02 ...

Page 5

... TTL levels the boot block programming lockout feature is again active. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see “ ...

Page 6

... The standard pin definition allows use of the JEDEC standard programming algorithm. If the alternate pin definition is used, the programming algo- rithm must be modified as shown in the Command Definition for Alternate Pin Definition table on page 8. sense power on delay: once 1049K–FLASH–11/02 ...

Page 7

... Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0. Voltage on RESET with Respect to Ground ...................................-0.6V to +13.5V 1049K–FLASH–11/02 AT49BV/LV008A(T)/8192A(T) (1) 1st Bus 2nd Bus 3rd Bus Cycle Cycle ...

Page 8

... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (1) 6th Bus Cycle Addr Data A555 10 ( A555 40 1049K–FLASH–11/02 ...

Page 9

... Standby Current CMOS SB1 Standby Current TTL SB2 CC ( Active Current Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH Note the erase mode mA. CC 1049K–FLASH–11/02 AT49BV/LV008A(T)/8192A(T) AT49LV008A(T)-70 AT49LV8192A(T)-70 N/A -40 ° ° C 3. RESET ( ...

Page 10

... ADDRESS ADDRESS VALID ACC t RO RESET HIGH Z OUTPUT OUTPUT - t after the address transition without impact on t ACC after the falling edge of CE without impact pF). L -90 Max Min Max 800 800 VALID . ACC after an address change CE ACC OE Units 1049K–FLASH–11/02 ...

Page 11

... Input Test Waveforms and Measurement Level Output Test Load Pin Capacitance MHz ° C (1) Symbol Typ OUT Note: 1. This parameter is characterized and is not 100% tested. 1049K–FLASH–11/02 AT49BV/LV008A(T)/8192A( < Max 6 12 Units Conditions OUT 11 ...

Page 12

... Address Hold Time AH t Chip Select Setup Time CS t Chip Select Hold Time CH t Write Pulse Width ( Data Setup Time Data, OE Hold Time DH OEH t Write Pulse Width High WPH AC Byte/Word Load Waveforms WE Controlled CE Controlled AT49BV/LV008A(T)/8192A(T) 12 Min Max Units 1049K–FLASH–11/02 ...

Page 13

... For chip erase, the address should be 5555. For sector erase, the address depends on what sector erased. (See note 4 under Command Definitions.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. 1049K–FLASH–11/02 AT49BV/LV008A(T)/8192A(T) PROGRAM CYCLE ...

Page 14

... Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. AT49BV/LV008A(T)/8192A(T) 14 (1) (1) Min Typ Max Min Typ Max 10 10 150 0 specification must be met by the toggling OEHP 1049K–FLASH–11/02 Units Units ...

Page 15

... Device Code: 22H (AT49BV/LV008A); 00A0H (AT49BV/LV8192A); 21H (AT49BV/LV008AT); 00A3H (AT49BV/LV8192AT) 6. Either one of the Product ID Exit commands can be used the alternate pin definition is used, 5555 should be replaced with A555, 2AAA should be replaced with 5AAA. 1049K–FLASH–11/02 AT49BV/LV008A(T)/8192A(T) (1) Boot Block Lockout Enable Algorithm (7) (7) (7) ...

Page 16

... AT49BV/LV008A(T)/8192A(T) 16 Ordering Code Package AT49LV008AT-70CI 48C1 AT49LV008A-70TI 40T AT49BV008AT-90CI 48C1 AT49BV008A-90TI 40T Ordering Code Package AT49LV8192A-70TI 48T AT49LV8192AT-70TI 48T AT49BV8192A-90TI 48T AT49BV8192AT-90TI 48T AT49BV8192AT-90CI 48C1 Package Type Operation Range Industrial (-40° to 85°C) Industrial (-40° to 85°C) Operation Range Industrial (-40° ...

Page 17

... Packaging Information 48C1 – CBGA Dimensions in Millimeters and (Inches). Controlling dimension: millimeters. 0.875 (0.034) REF 0.75 (0.0295) BSC NON-ACCUMULATIVE 2325 Orchard Parkway San Jose, CA 95131 R 1049K–FLASH–11/02 AT49BV/LV008A(T)/8192A(T) 7.10(0.280) 6.90(0.272 7.10(0.280) 6.90(0.272) TOP VIEW 5.25 (0.207 0.75 (0.0295) BSC ...

Page 18

... A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 E 9.90 10.00 10.10 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.50 BASIC DRAWING NO. NOTE Note 2 Note 2 10/18/01 REV. 40T B 1049K–FLASH–11/02 ...

Page 19

... This package conforms to JEDEC reference MO-142, Variation DD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 1049K–FLASH–11/02 AT49BV/LV008A(T)/8192A(T) PIN SEATING PLANE ...

Page 20

... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...

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