M29W040B90N6T Micron Technology Inc, M29W040B90N6T Datasheet - Page 6

• Manufacturer Part Number: M29W040B90N6T
• Manufacturer: Micron Technology Inc

Specifications of M29W040B90N6T

• Lead Free Status / Rohs Status: Supplier Unconfirmed

M29W040B
Table 5. Commands
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until the Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
6/20
Read/Reset
Auto Select
Program
Unlock Bypass
Unlock Bypass
Program
Unlock Bypass Reset
Chip Erase
Block Erase
Erase Suspend
Erase Resume
Command
6+
1
3
3
4
3
2
2
6
1
1
Addr Data
555
555
555
555
555
555
X
X
X
X
X
1st
AA
AA
AA
AA
AA
AA
F0
A0
B0
90
30
Addr
2AA
2AA
2AA
2AA
2AA
2AA
PA
X
2nd
Data
PD
55
55
55
55
00
55
55
Addr
555
555
555
555
555
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ‘1’. All previous
data is lost.
X
Bus Write Operations
3rd
Data
F0
A0
90
20
80
80
Addr Data Addr
555
555
PA
4th
PD
AA
AA
2AA
2AA
5th
Data
55
55
Addr Data
555
BA
6th
10
30