M29W040B90N6T Micron Technology Inc, M29W040B90N6T Datasheet - Page 3

• Manufacturer Part Number: M29W040B90N6T
• Manufacturer: Micron Technology Inc

Specifications of M29W040B90N6T

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 2. Absolute Maximum Ratings
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
Table 3. Uniform Block Addresses, M29W040B
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A18). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
#
7
6
5
4
3
2
1
0
Symbol
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
V
T
T
V
V
IO
BIAS
T
STG
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
CC
ID
A
(Kbytes)
(2)
Size
64
64
64
64
64
64
64
64
Ambient Operating Temperature (Temperature Range Option 1)
Ambient Operating Temperature (Temperature Range Option 6)
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Identification Voltage
Address Range
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
(1)
Parameter
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
V
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
Supply Voltage is less than the Lockout Voltage,
V
cidentally damaging the data during power-up,
power-down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
V
all voltage measurements.
CC
LKO
SS
Ground. The V
Supply Voltage. The V
. This prevents Bus Write operations from ac-
CC
IH
Supply Voltage pin and the V
, all other pins are ignored.
CC3
SS
.
Ground is the reference for
–0.6 to 13.5
–50 to 125
–65 to 150
–40 to 85
–0.6 to 4
–0.6 to 4
0 to 70
Value
CC
Supply Voltage
M29W040B
SS
Ground
Unit
°C
°C
°C
°C
V
V
V
3/20
CC