P89C51RB2HBA NXP Semiconductors, P89C51RB2HBA Datasheet - Page 11

• Manufacturer Part Number: P89C51RB2HBA
• Manufacturer: NXP Semiconductors

Specifications of P89C51RB2HBA

• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 33MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 512Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

*
# SFRs are modified from or added to the 80C51 SFRs.
– Reserved bits.
Philips Semiconductors
SPECIAL FUNCTION REGISTERS (CONTINUED)
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an
on-chip oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. Minimum and maximum
high and low times specified in the data sheet must be observed.
This device is configured at the factory to operate using 6 clock
periods per machine cycle, referred to in this datasheet as “6 clock
mode”. (This yields performance equivalent to twice that of standard
80C51 family devices). It may be optionally configured on
commercially-available EPROM programming equipment to operate
at 12 clocks per machine cycle, referred to in this datasheet as
“12 clock mode”. Once 12 clock mode has been configured, it
cannot be changed back to 6 clock mode.
2002 May 24
SYMBOL
PSW*
RCAP2H#
RCAP2L#
SADDR#
SADEN#
SBUF
SCON*
SP
TCON*
T2CON*
T2MOD#
TH0
TH1
TH2#
TL0
TL1
TL2#
TMOD
WDTRST
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
SFRs are bit addressable.
Program Status Word
Timer 2 Capture High
Timer 2 Capture Low
Slave Address
Slave Address Mask
Serial Data Buffer
Serial Control
Stack Pointer
Timer Control
Timer 2 Control
Timer 2 Mode Control
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
Timer Low 1
Timer Low 2
Timer Mode
Watchdog Timer Reset
DESCRIPTION
ADDRESS
DIRECT
CDH
CCH
D0H
CBH
CAH
C8H
C9H
8CH
8DH
A9H
B9H
99H
98H
81H
88H
8AH
8BH
89H
A6H
MSB
SM0/FE
GATE
TF1
TF2
CY
CF
D7
9F
8F
–
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
EXF2
SM1
TR1
C/T
AC
CE
D6
9E
8E
–
RCLK
8
SM2
TF0
CD
D5
9D
8D
M1
F0
–
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (12 oscillator periods in 6 clock mode, or 24 oscillator
periods in 12 clock mode), while the oscillator is running. To ensure a
good power-on reset, the RST pin must be high long enough to allow
the oscillator time to start up (normally a few milliseconds) plus two
machine cycles. At power-on, the voltage on V
come up at the same time for a proper start-up. Ports 1, 2, and 3 will
asynchronously be driven to their reset condition when a voltage
above V
The value on the EA pin is latched when RST is deasserted and has
no further effect.
TCLK
REN
RS1
TR0
CC
M0
D4
9C
8C
–
IH1
(min.) is applied to RESET.
EXEN2
GATE
RS0
TB8
IE1
CB
D3
9B
8B
–
P89C51RB2/P89C51RC2/
RB8
TR2
C/T
OV
IT1
CA
D2
9A
8A
–
T2OE
C/T2
IE0
P89C51RD2Hxx
D1
C9
M1
F1
99
89
TI
CP/RL2
DCEN
IT0
LSB
D0
C8
M0
CC
98
88
RI
P
and RST must
00000000B
00H
00H
00H
00H
xxxxxxxxB
00H
07H
00H
00H
xxxxxx00B
00H
00H
00H
00H
00H
00H
00H
Product data
RESET
VALUE