SL811HST Cypress Semiconductor Corp, SL811HST Datasheet - Page 2

• Manufacturer Part Number: SL811HST
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL811HST

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

2.2
The SL811HS microprocessor interface provides an 8-bit
bidirectional data path along with appropriate control lines to
interface to external processors or controllers. Programmed
I/O or memory mapped I/O designs are supported through the
8-bit interface, chip select, read and write input strobes and a
single address line, A0.
Access to memory and control register space is a simple two
step process, requiring an address Write with A0 = “0,”
followed by a register/memory Read or Write cycle with
address line A0 = “1.”
In addition, a DMA bi-directional interface in slave mode is
available with handshake signals such as nDRQ, nDACK,
nWR, nRD, nCS and INTRQ.
The SL811HS Write or Read operation terminates when either
nWR or nCS goes inactive. For devices interfacing to the
SL811HS that deactivate the Chip Select nCS before the Write
nWR, the data hold timing should be measured from the nCS
and will be the same value as specified. Thus, both Intel
Motorola-type CPUs can work easily with the SL811HS
without any external glue logic requirements.
2.3
In applications that require transfers of large amounts of data
such as scanner interfaces, the SL811HS provides a DMA in-
terface. This interface supports DMA read or write transfers to
the SL811HS internal RAM buffer through the microprocessor
data bus via two control lines (nDRQ - Data Request and
nDACK - Data Acknowledge) along with the nWR line and con-
trols the data flow into the SL811HS. The SL811HS has a
count register that allows programmable block sizes to be se-
lected for DMA transfer. The control signals, both nDRQ and
nDACK, are designed to be compatible with standard DMA
interfaces.
2.4
The SL811HS interrupt controller provides a single output
signal (INTRQ) that can be activated by a number of program-
mable events that may occur as result of USB activity. Control
and status registers are provided to allow the user to select
single or multiple events, which will generate an interrupt
(assert INTRQ), and let the user view interrupt status. The
interrupts can be cleared by writing to the appropriate register
(the Interrupt Status Register).
2.5.1.1 Auto Address Increment Example
If filling the data buffer that is configured to be at address 10h
you would do the following:
Document 38-08008 Rev. *B
1. Write 10h to SL811HS with A0 LOW. This sets the memory
2. Write the first data byte into address 10h by doing a write
3. Now the internal RAM address pointer is set to 11h so by
address that will be used for the next operation.
operation with A0 HIGH. An example would be if you were
doing a Get Descriptor, the first byte that would be sent to
the device would be 80h (bmRequestType) so you would
write 80h to address 10h.
doing another write with A0 HIGH, RAM address location
11h will be written with the data. Continuing with the Get
Data Port, Microprocessor Interface
DMA Controller (slave mode only)
Interrupt Controller
®
- and
2.5
The SL811HS contains 256 bytes of internal memory used for
USB data buffers, control registers and status registers. When
in master mode (host mode), the memory is defined where the
first 16 bytes are registers and the remaining 240 bytes are
used for USB data buffers. When in slave mode (peripheral
mode), the first 64 bytes are used for the 4 endpoint control
and status registers along with the various other registers. This
leaves 192 bytes of endpoint buffer space for USB data
transfers.
Access to the registers and data memory is through the 8-bit
external microprocessor data bus, in either indexed or direct
addressing. Indexed mode uses the Auto Address Increment
mode described in Section 2.5.1 Auto Address Increment
Mode, where direct addressing is used to read/write to an
individual address.
USB transactions are automatically routed to the memory
buffer that is configured for that transfer. Control registers are
provided, so that pointers and block sizes in buffer memory
can be determined and allocated.
Host mode memory map
2.5.1
The SL811HS supports auto increment mode to reduce read
and write memory cycles. In this mode, the microcontroller
needs to set up the address only once. Whenever any subse-
quent DATA is accessed, the internal address counter will ad-
vance to the next address location.
The advantage of auto address increment mode is that it
reduces the number of SL811HS memory Read/Write cycles
required to move data to/from the device. For example, trans-
ferring 64-bytes of data to/from SL811HS using auto increment
mode, will reduce the number of cycles to 1 Address Write and
64 Read/Write Data cycles, compared to 64 Address Writes
and 64 Data Cycles for Random Access.
4. Step 3 would then be repeated until all of the required bytes
240 bytes
16 bytes
Descriptor example a 06h would be written to address 11h
for the bRequest value.
have been written necessary for a transfer. If auto-incre-
menting is not used you would write the address value each
time before writing the data as shown in step 1.
Buffer Memory
Auto Address Increment Mode
0x00 – 0x0F Control
and status registers
0x10 – 0xFF
USB data buffer
Figure 2-2. Memory Map
Peripheral mode memory map
192 bytes
64 bytes
Control/status registers
control/status registers
0x00 – 0x39
and endpoint
0x40 – 0xFF
USB data buffer
SL811HS
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