MC68HC705C8ACB Freescale Semiconductor, MC68HC705C8ACB Datasheet - Page 155

• Manufacturer Part Number: MC68HC705C8ACB
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705C8ACB

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 2.1MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 304Byte
• # I/os (max): 24
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Not Compliant

12.3.1 Inherent
12.3.2 Immediate
12.3.3 Direct
12.3.4 Extended
MC68HC705C8A — Rev. 3
MOTOROLA
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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Instruction Set
Addressing Modes
Technical Data
Instruction Set