AM29F100T-90SC AMD (ADVANCED MICRO DEVICES), AM29F100T-90SC Datasheet - Page 7

• Manufacturer Part Number: AM29F100T-90SC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29F100T-90SC

• Lead Free Status / Rohs Status: Not Compliant

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend:
L = Logic Low = V
Notes:
1. Addresses are A15:A0 in word mode (BYTE# = V
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
Read
Write
Standby
Output Disable
Hardware Reset
Temporary Sector
Unprotect
tection/Unprotection” section.
Operation
IL
, H = Logic High = V
IH
V
CC
. The BYTE# pin determines
CE#
± 0.5 V
X
X
L
L
L
Table 1. Am29F100 Device Bus Operations
IL
OE# WE#
IH
. CE# is the power
H
X
H
X
X
L
, V
ID
= 12.0 0.5 V, X = Don’t Care, A
H
X
H
X
X
L
V
IH
CC
RESET#
), A15:A-1 in byte mode (BYTE# = V
V
± 0.5 V
Am29F100
H
H
H
L
ID
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. The appropriate device bus operations table
lists the inputs and control levels required, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
Addresses
(Note 1)
A
A
A
X
X
X
IN
IN
IN
IL
IN
, and OE# to V
= Addresses In, D
High-Z
High-Z
High-Z
DQ0–
D
DQ7
D
D
OUT
IN
IN
IL
).
CC1
BYTE#
High-Z
High-Z
High-Z
D
= V
IH
D
D
OUT
.
IN
IN
IN
IH
in the DC Characteristics
= Data In, D
DQ8–DQ14 = High-Z,
DQ8–DQ15
DQ15 = A-1
BYTE#
High-Z
High-Z
High-Z
High-Z
OUT
= V
IL
= Data Out
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