AM29F100T-90SC AMD (ADVANCED MICRO DEVICES), AM29F100T-90SC Datasheet - Page 2

• Manufacturer Part Number: AM29F100T-90SC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29F100T-90SC

• Lead Free Status / Rohs Status: Not Compliant

GENERAL DESCRIPTION
The Am29F100 is a 1 Mbit, 5.0 Volt-only Flash memory
organized as 131,072 bytes or 65,536 words. The
Am29F100 is offered in 44-pin SO and 48-pin TSOP
packages. Word-wide data appears on DQ0-DQ15;
byte-wide data on DQ0-DQ7. The device is designed to be
programmed in-system with the standard system 5.0 Volt
V
erase operations. The device can also be programmed or
erased in standard EPROM programmers.
The standard device offers access times of 70, 90, 120,
and 150 ns, allowing high-speed microprocessors to op-
erate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This invokes the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This invokes the Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
2
CC
supply. A 12.0 volt V
PP
is not required for program or
Am29F100
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The Erase Suspend feature enables the system to put
erase on hold for any period of time to read data from,
or program data to, a sector that is not being erased.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The hardware data protection measures include a
low V
during power transitions. The hardware sector pro-
tection feature disables both program and erase
operations in any combination of the sectors of mem-
ory, and is implemented using standard EPROM
programmers. The temporary sector unprotect fea-
ture allows in-system changes to protected sectors.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in this
mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t l e v e l s o f q u a l i ty, re l i a b il i ty, a n d c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection.
CC
detector automatically inhibits write operations