A54SX08A-FTQ100 MICROSEMI, A54SX08A-FTQ100 Datasheet - Page 7

• Manufacturer Part Number: A54SX08A-FTQ100
• Manufacturer: MICROSEMI

Specifications of A54SX08A-FTQ100

• Family Name: SX-A
• Number Of Usable Gates: 8000
• Number Of Logic Blocks/elements: 768
• # Registers: 512
• # I/os (max): 81
• Frequency (max): 172MHz
• Process Technology: 0.25um/0.22um (CMOS)
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 512
• Device System Gates: 12000
• Propagation Delay Time: 1.7ns
• Operating Supply Voltage (min): 2.25V
• Operating Supply Voltage (max): 2.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Routing Resources
The routing and interconnect resources of SX-A devices
are in the top two metal layers above the logic modules
(Figure 1-1 on page
thus enabling the entire floor of the device to be
spanned with an uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using the Actel patented metal-to-metal programmable
antifuse interconnect elements. The antifuses are
normally open circuits and, when programmed, form a
permanent low-impedance connection.
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters
Figure 1-6 on page
dramatically reduces the number of antifuses required to
complete a circuit, ensuring the highest possible
performance, which is often required in applications such
as fast counters, state machines, and data path logic. The
interconnect elements (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring
R-Cell in a given SuperCluster. DirectConnect uses a
hardwired signal path requiring no programmable
Figure 1-4 • Cluster Organization
DirectConnect
Internal Logic
1-1), providing optimal use of silicon,
1-4). This routing architecture also
CLKA,
Input
CLKB,
HCLK
Cluster 1
CKS
S0
(Figure 1-5 on page 1-4
Type 1 SuperCluster
Data Input
Routed
R-Cell
CKP
S1
D
Cluster 1
PRE
CLR
Q
and
Y
v5.3
interconnection to achieve its fast signal propagation
time of less than 0.1 ns.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster, and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect path, delivering a maximum pin-to-pin
propagation time of 0.3 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. The Actel segmented routing structure provides
a variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
100% automatic place-and-route software to minimize
signal propagation delays.
The general system of routing tracks allows any logic
module in the array to be connected to any other logic
or I/O module. Within this system, most connections
typically require three or fewer antifuses, resulting in
fast and predictable performance.
The unique local and general routing structure featured
in SX-A devices allows 100% pin-locking with full logic
utilization, enables concurrent printed circuit board
(PCB) development, reduces design time, and allows
designers to achieve performance goals with minimum
effort.
D0
D1
D2
D3
DB
Cluster 2
Type 2 SuperCluster
A0 B0
C-Cell
Sa
Cluster 1
A1 B1
Sb
Y
SX-A Family FPGAs
1-3