A54SX08A-FTQ100 MICROSEMI, A54SX08A-FTQ100 Datasheet - Page 106

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A54SX08A-FTQ100

Manufacturer Part Number
A54SX08A-FTQ100
Description
Manufacturer
MICROSEMI
Datasheet

Specifications of A54SX08A-FTQ100

Family Name
SX-A
Number Of Usable Gates
8000
Number Of Logic Blocks/elements
768
# Registers
512
# I/os (max)
81
Frequency (max)
172MHz
Process Technology
0.25um/0.22um (CMOS)
Operating Supply Voltage (typ)
2.5V
Logic Cells
512
Device System Gates
12000
Propagation Delay Time
1.7ns
Operating Supply Voltage (min)
2.25V
Operating Supply Voltage (max)
2.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A54SX08A-FTQ100
Manufacturer:
Microsemi SoC
Quantity:
10 000
4 -2
Previous Version Changes in Current Version (v5 . 3)
SX-A Family FPGAs
(continued)
v2.0.1
v4.0
v3.0
Table 2-12
The was updated.
The
Table 2-13
Table 2-13
All timing tables were updated.
The
Design Theft" section
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"Sample Path Calculations"
"Ordering Information" section
"Temperature Grade Offering" section
Figure 1-1 • SX-A Family Interconnect Elements
“"Clock Resources"
Table 1-1 • SX-A Clock Resources
"User Security" section
"I/O Modules" section
Table 1-2 • I/O Features
Table 1-3 • I/O Characteristics for All I/O Configurations
Table 1-4 • Power-Up Time at which I/Os Become Active
Figure 1-12 • Device Selection Wizard
"Boundary-Scan Pin Configurations and Functions" section
Table 1-9 • Device Configuration Options for Probe Capability (TRST Pin Reserved)
"SX-A Probe Circuit Control Pins" section
"Design Considerations" section
Figure 1-13 • Probe Setup
Design Environment
Figure 1-13 • Design Flow
"Absolute Maximum Ratings*" section
"Recommended Operating Conditions" section
"Electrical Specifications" section
"2.5V LVCMOS2 Electrical Specifications" section
"SX-A Timing Model"
"Pin Description" section
"Design Environment" section
"I/O Modules"
"Actel Secure Programming Technology with FuseLock™ Prevents Reverse Engineering and
"SX-A Timing Model" section
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"Sample Path Calculations"
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Table 1-2 • I/O Features
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v5.3
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"Timing Characteristics" section
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have new timing
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