W320-04X Silicon Laboratories Inc, W320-04X Datasheet - Page 4

• Manufacturer Part Number: W320-04X
• Manufacturer: Silicon Laboratories Inc

Specifications of W320-04X

• Lead Free Status / Rohs Status: Not Compliant

Rev 1.0, November 25, 2006
Serial Data Interface (SMBus)
To enhance the flexibility and function of the clock synthesizer,
a two-signal SMBus interface is provided according to SMBus
specification. Through the Serial Data Interface, various
device functions such as individual clock output buffers, can
be individually enabled or disabled. W320-04 supports both
block read and block write operations.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte, (most significant bit first) with the
Data Byte Configuration Map
Data Byte 0: Control Register (0 = Enable, 1 = Disable)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Start
1 bit
bit
Bit
Slave Address
1 1 0 1 0 0 1 0
5, 6, 7, 10,
11, 12, 13,
16, 17, 18,
33, 35
–
35
44, 45, 48,
49, 51, 52
10, 11, 12,
13, 16, 17,
18
–
–
–
Affected
7 bits
Pin#
From Master to Slave
From Slave to Master
PCI [0:6]
CPU[2:0]
3V66[1:0]
TBD
3V66_1/VCH
CPU [2:0]
CPU# [2:0]
PCI [6:0]
–
–
–
R/W 0/1 A
1
Name
1
0 0 0 0 0 0 0 0
Command
Code
8 bits
Figure 1. An Example of a Block Write
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
TBD
VCH Select 66 MHz/48 MHz
0 = 66 MHz, 1 = 48 MHz
CPU_STOP#
Reflects the current value of the external CPU_STOP# pin
PCI_STOP#
(Does not affect PCI_F [2:0] pins)
S2
Reflects the value of the S2 pin sampled on power-up
S1
Reflects the value of the S1 pin sampled on power-up
S0
Reflects the value of the S1 pin sampled on power-up
A Byte Count = N A Data Byte 0 A
1
Figure 1.
8 bits
ability to stop after any complete byte has been transferred.
Indexed bytes are not allowed.
A block write begins with a slave address and a WRITE
condition. The R/W bit is used by the SMBus controller as a
data direction bit. A zero indicates a WRITE condition to the
clock device. The slave receiver address is 11010010 (D2h).
A command code of 0000 0000 (00h) and the byte count bytes
are required for any transfer. After the command code, the
core logic issues a byte count which describes number of
additional bytes required for the transfer, not including the
command code and byte count bytes. For example, if the host
has 20 data bytes to send, the first byte would be the number
20 (14h), followed by the 20 bytes of data. The byte count byte
is required to be a minimum of 1 byte and a maximum of 32
bytes It may not be 0. Figure 1 shows an example of a block
write.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
Description
1
8 bits
1
. . . Data Byte N-1 A Stop
8 bits
R/W
R
R/W
R
R/W
R
R
R
Type
W320-04
Page 4 of 16
0
0
0
N/A
N/A
N/A
N/A
N/A
Power On
Default
1 1 bit
bit