83336-22 Peregrine Semiconductor, 83336-22 Datasheet - Page 4

• Manufacturer Part Number: 83336-22
• Description: IC PLL INTEGER-N 3GHZ 44CQFJ
• Manufacturer: Peregrine Semiconductor
• Series: UltraCMOS™r
• Type: PLL Clock Driverr

Specifications of 83336-22

• Input: Clock
• Output: Clock
• Frequency - Max: 3GHz
• Voltage - Supply: 2.85 V ~ 3.15 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 44-CLCC Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 1. Pin Descriptions (continued)
Note 1:
Note 2:
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 13
(44-lead
Pin No.
CQFJ)
N/A
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
All V
V
outputs.
All digital input pins have 70 kΩ pull-down resistors to ground.
DD
-f
DD
p
f
V
Dout
V
Cext
V
PD_D
PD_U
V
f
GND
GND
f
LD
Enh
NC
and V
p
c
r
Name
pins are connected by diodes and must be supplied with the same positive voltage level.
DD
DD
DD
DD
Pin
-f
-f
p
c
DD
-f
p
are used to power the f
ALL
ALL
Serial,
Parallel
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
Serial,
Parallel
ALL
Interface
Mode
Output
(Note 1)
Output
(Note 1)
Output
(Note 1)
Output
(Note 1)
Output
Input
Output
Input
Type
p
and f
Monitor pin for main divider output. Switching activity can be disabled through enhancement
register programming or by floating or grounding V
V
Data Out. The MSEL signal and the raw prescaler output are available on Dout through
enhancement register programming.
Same as pin 1.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
Same as pin 1.
PD_D is pulse down when f
PD_U is pulse down when f
V
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
Ground.
Ground.
Reference frequency input.
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
No connection.
c
DD
DD
outputs and can alternatively be left floating or connected to GND to disable the f
for f
for f
c
p
. Can be left floating or connected to GND to disable the f
can be left floating or connected to GND to disable the f
p
c
leads f
leads f
Document No. 70-0137-02 │ UltraCMOS™ RFIC Solutions
c
p
.
.
Description
DD
pin 31.
c
DD
output.
p
pin 38.
output.
Product Specification
PE83336
p
and f
c