DS90CF386MTDX National Semiconductor, DS90CF386MTDX Datasheet - Page 11
![](/photos/31/35/313579/56pin_tssop_sml.jpg)
DS90CF386MTDX
Manufacturer Part Number
DS90CF386MTDX
Description
Manufacturer
National Semiconductor
Datasheet
1.DS90CF386MTDX.pdf
(18 pages)
Specifications of DS90CF386MTDX
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS90CF386MTDX
Manufacturer:
NS/国半
Quantity:
20 000
Part Number:
DS90CF386MTDX NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
Company:
Part Number:
DS90CF386MTDX/NOPB
Manufacturer:
TI
Quantity:
3 132
Part Number:
DS90CF386MTDX/NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
V
GND
CC
CC
CC
DS90CF386 MTD56 Package Pin Descriptions—24-Bit FPD Link Receiver
DS90CF366 MTD48 Package Pin Descriptions—18-Bit FPD Link Receiver
DS90CF386 — 64 ball FBGA package Pin Descriptions —
FPD Link Receiver
Pin Name
Pin Name
Pin Name
CC
CC
CC
CC
I/O No
I/O No
I/O No
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME,
28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
3 Positive LVDS differentiaI data inputs.
3 Negative LVDS differential data inputs.
1 Positive LVDS differential clock input.
1 Negative LVDS differential clock input.
1 TTL Ievel clock output. The falling edge acts as data strobe.
1 TTL level input. When asserted (low input) the receiver outputs are low.
4 Power supply pins for TTL outputs.
5 Ground pins for TTL outputs.
1 Power supply for PLL.
2 Ground pin for PLL.
1 Power supply pin for LVDS inputs.
3 Ground pins for LVDS inputs.
4 Positive LVDS differentiaI data inputs.
4 Negative LVDS differential data inputs.
1 Positive LVDS differential clock input.
1 Negative LVDS differential clock input.
1 TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
1 TTL level input. When asserted (low input) the receiver outputs are low.
4 Power supply pins for TTL outputs.
5 Ground pins for TTL outputs.
4
4
1
1
1
1
4
5
1
2
1
3
.
.
.
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
11
Description
Description
Description
www.national.com