DS90CF386MTDX National Semiconductor, DS90CF386MTDX Datasheet
DS90CF386MTDX
Specifications of DS90CF386MTDX
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DS90CF386MTDX Summary of contents
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... Block Diagrams DS90CF386 Order Number DS90CF386MTD or DS90CF386SLC See NS Package Number MTD56 or SLC64A TRI-STATE® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS90CF386/DS90CF366 This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Output Voltage LVDS Receiver Input Voltage Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec for TSSOP) Solder Reflow Temperature ...
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Symbol Parameter ICCRZ Receiver Supply Current Power Down Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these ...
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AC Timing Diagrams FIGURE 2. “16 Grayscale” Test Pattern www.national.com FIGURE 1. “Worst Case” Test Pattern (DS90CF386)(Note 5, 4 10108502 10108512 Note 6, Note 7, Note 8) ...
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FIGURE 3. “16 Grayscale” Test Pattern Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD ...
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FIGURE 5. DS90CF386/DS90CF366 (Receiver) Setup/Hold and High/Low Times FIGURE 6. DS90CF386/DS90CF366 (Receiver) Clock In to Clock Out Delay FIGURE 7. DS90CF386/DS90CF366 (Receiver) Phase Lock Loop Set Time www.national.com 10108505 10108506 6 10108507 ...
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FIGURE 8. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF386 FIGURE 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF366 FIGURE 10. DS90CF386/DS90CF366 (Receiver) Power Down Delay 10108508 7 10108509 10108510 www.national.com ...
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FIGURE 11. DS90CF386 (Receiver) LVDS Input Strobe Position www.national.com 8 10108525 ...
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FIGURE 12. DS90CF366 (Receiver) LVDS Input Strobe Position 9 10108526 www.national.com ...
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos—Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note ISI ...
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DS90CF386 MTD56 Package Pin Descriptions—24-Bit FPD Link Receiver Pin Name I RxIN Positive LVDS differentiaI data inputs. RxIN− Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This includes: 8 Red, ...
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Pin Name I PLL Power supply for PLL. CC PLL GND I 2 Ground pin for PLL. LVDS Power supply pin for LVDS inputs. CC LVDS GND I 3 Ground pins for ...
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By Pin E8 RxOUT0 F1 RxOUT23 F2 RxOUT26 RxIN1- F5 RxIN2+ F6 PLL GND F7 PLL VCC RxOUT25 LVDS GND G4 RxIN1+ G5 RxIN2- G6 RxIN3- G7 LVDS GND G8 PLL ...
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Pin Diagrams for TSSOP Packages DS90CF386MTD Applications Information POWER SEQUENCING AND POWERDOWN MODE Outputs of the transmitter remain in TRI-STATE until the pow- er supply reaches 2V. Clock and data outputs will begin to toggle 10 ms after V has ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Dimensions shown in millimeters only Order Number DS90CF386MTD NS Package Number MTD56 Dimensions shown in millimeters only ...
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Package www.national.com Dimensions show in millimeters Order Number DS90CF386SLC NS Package Number SLC64A 16 ...
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Notes 17 www.national.com ...
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