TXC-06412BROG Transwitch Corporation, TXC-06412BROG Datasheet - Page 203

• Manufacturer Part Number: TXC-06412BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BROG

• Lead Free Status / Rohs Status: Compliant

2 0 3 o f 2 26
Offset
0x0000
Offset
0x0000
0
4 - 1
5
6
10 - 7
11
0
Bits
Bits
EnablePRBSGenerator
PRBSGeneratorChannel
InvertPRBSGeneratorOutput
EnablePRBSAnalyzer
PRBSAnalyzerChannel
InvertPRBSAnalyzerOutput
SerDes_LoadConfig
Table 66: CDR/CS Configuration
Name
Name
Table 65: PRBS Configuration
- Memory Maps and Bit Descriptions -
Init
Init
0x0
0x0
0x0
0x1
0x0
0x1
0x0
The PRBS generator at the cross connect is enabled when 0x1, dis-
abled when 0x0.
Range 0 to 11
Path on which PRBS is inserted.
The output of the PRBS generator is inverted when 0x1.
The PRBS analyzer at the cross connect is enabled when 0x1, dis-
abled when 0x0.
Range 0 to 11
Path on which PRBS is received.
The received bits are inverted before they are analyzed by the PRBS
analyzer when 0x1.
Writing 0x1 to this register will start the transmission of the con-
trol signals to the SerDes.
When the transmission is finished this register is reset to its
default value.
Writing 0x0 to the register is ignored.
The following settings are transmitted:
•
•
•
•
•
•
•
•
•
•
•
•
CDR_CS_Setup.TxPowerDown
CDR_CS_Setup.RxPowerDown1
CDR_CS_Setup.RxPowerDown2
CDR_CS_Setup.ToplevelPowerDown
CDR_CS_Setup.OC3NotOC12
PLL_Control.TxPLL_Cap_Enable
PLL_Control.RxPLL_Cap_Enable
PLL_Control.TxPLL_PowerDown
PLL_Control.RxPLL_PowerDown
PLL_Control.CDRTune[4:0]
PLL_Control.PLLTune
All settings configured via the indirect access register
(CDR_CS_Setup.Indirect_AccessData and
Common_Config.IndirectAccessMode)
(T_ANALOG_Common_Config)
(T_XConnectPRBSControl)
Description
Description
PRELIMINARY TXC-06412B-MB, Ed. 2
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005