SL72P4M128M8M-B05AYU STEC, SL72P4M128M8M-B05AYU Datasheet - Page 9

• Manufacturer Part Number: SL72P4M128M8M-B05AYU
• Manufacturer: STEC

Specifications of SL72P4M128M8M-B05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 9Gb
• Access Time (max): 600ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 4.77A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P4M128M8M-B05AY(W)U
INPUT ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
Input DC Logic Levels
All voltages referenced to VSS.
Input AC Logic Levels
All voltages referenced to VSS.
IDD SPECIFICATIONS AND CONDITIONS
IDD specifications are tested after the device is properly
initialized. 0°C ≤ TOPR ≤ +55°C. VDD = +1.8V ±0.1V, VDDQ =
+1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/ 2.
Input slew rate is specified by AC Parametric Test Conditions.
IDD parameters are specified with ODT disabled. Data bus
consists of DQ, DQS, and DQS#. IDD values must be met with
all combinations of EMR bits 10 and 11.
Definitions for IDD Conditions:
•
•
General IDD Parameters
IDD7 Conditions
IDD7: Operating Current, specifies detailed timing requirements
for IDD7. Changes will be required if timing parameter changes
are made to the specification.
LOW is defined as VIN≤VIL (AC) (MAX)
HIGH is defined as VIN≥VIH (AC) (MIN)
Parameter
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Speed Grade
DDR2-400
Parameter
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
IDD Parameter
CL (IDD)
tRCD (IDD)
tRC (IDD)
tRRD (IDD)
tCK (IDD)
tRAS MIN (IDD)
tRAS MAX (IDD)
tRP (IDD)
tRFC (IDD)
IDD7 Timing Patterns
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
VIH(AC)
VIH(DC)
Symbol
Symbol
VIL(DC)
VIL(AC)
Document Part Number 61000-02973-106 July 2007 Page 9
DDR2-400
•
•
•
•
IDD7 Operating Current
All Bank Interleave Read operation; legend: A = active; RA =
read auto precharge; D = deselect
All device banks are being interleaved at minimum tRC (IDD)
without violating tRRD (IDD) using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTs. IOUT
= 0mA.
70,000
VREF + 250
VREF + 125
105
7.5
15
55
15
40
STABLE is defined as inputs stable at a HIGH or LOW
level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as inputs changing between
HIGH and LOW every other clock cycle (once per two
clocks) for address and control signals
Switching is defined as inputs changing between HIGH
and LOW every other data transfer (once per clock) for
DQ signals not including masks or strobes
3
5
-300
Min
Min
–
Units
tCK
VDDQ + 300 mV
ns
ns
ns
ns
ns
ns
ns
ns
VREF - 250
VREF - 125
Max
Max
-
Units
Units
240-PIN RDIMM
mV
mV
mV