SL72P4M128M8M-B05AYU STEC, SL72P4M128M8M-B05AYU Datasheet

SL72P4M128M8M-B05AYU

Manufacturer Part Number

SL72P4M128M8M-B05AYU

Description

Manufacturer

STEC

Datasheet

1.SL72P4M128M8M-B05AYU.pdf (17 pages)

Specifications of SL72P4M128M8M-B05AYU

Main Category

DRAM Module

Sub-category

DDR2 SDRAM

Module Type

240RDIMM

Device Core Size

72b

Organization

128Mx72

Total Density

9Gb

Access Time (max)

600ps

Maximum Clock Rate

200MHz

Operating Supply Voltage (typ)

1.8V

Operating Current

4.77A

Number Of Elements

Operating Supply Voltage (max)

1.9V

Operating Supply Voltage (min)

1.7V

Operating Temp Range

0C to 55C

Operating Temperature Classification

Commercial

Pin Count

240

Mounting

Socket

Lead Free Status / Rohs Status

Compliant

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128M X 72 Bit (1GB) 240-Pin DDR2 Registered RDIMM ECC (PC2-3200) Very Low Profile (VLP) 1 Rank x 4; RoHS Compliant

GENERAL DESCRIPTION

The SL72P4M128M8M-B05AY(W)U is a 128M x 72 bit (1GB)

240-pin Double Data Rate 2 (DDR2) Registered Dual In-line

Memory Module (RDIMM) with ECC.

The module consists of eighteen CMOS 32M x 4 bit x 4 bank

DDR2 SDRAMs in lead-free BGA packages mounted in 1 rank

on a 240-pin glass epoxy substrate. The user has the option

of choosing industrial temperature rated SDRAM components.

A serial EEPROM using the two pin I

mounted to provide for the Serial Presence Detects (SPD).

Decoupling capacitors are mounted across the power supply.

FEATURES

ORDERING INFORMATION

Note: Adding the second (W) to the part number selects the

module with industrial temperature rated components.

240-PIN RDIMM ILLUSTRATION

Part Number

SL72P4M128M8M-B05AY(W)U

• PC2-3200 Compliant

• 240-Pin RDIMM form factor

• Industrial operating temperature option:

• Average Refesh Period 7.8us at lower then TCASE

• VDD=VDDQ=1.8V + 0.1V

• VDDSPD=1.7V to 3.6V

• DDR2 architecture: Two data accesses per clock cycle,

(DDR2-400 200MHz-5ns@CL-t

(W) = -40

JEDEC standard 1.8V I/O (SSTL_18 compatible)

differential clock inputs (CK, /CK), bi-directional

differential data strobe (DQS, /DQS), Off-Chip Driver

(OCD) Impedance Adjustment, On Die Termination

(ODT), On Chip Delay Locked Loop (DLL); four-bit

prefetch architecture

C, 3.9us at 85

C to 95

C < TCASE < 95

C (Ambient)

RCD

-t

MHz

200

C protocol is also

: 3-3-3)

Bandwidth

3.2 GB/s

EEPROM

Document Part Number 61000-02973-106 July 2007 Page 1

SL72P4M128M8M-B05AY(W)U

PLL

Damping resistors are added in series for DQ, DQS, and DM

signals. A PLL supplies clocks to the DDR2 SDRAMs from

one clock input.

All control and address signals are re-driven through registers

to the DDR2 SDRAM devices. The control/address input

signals are latched in the register on one rising clock edge

and sent to the SDRAM devices on the following rising clock

edge (data access is delayed by one clock).

The module has gold edge connections and is intended for

mounting into 240-pin RDIMM edge connector sockets keyed

for 1.8V.

• Commands entered on each rising CK edge; DQS-

• Four internal component banks for concurrent

• Concurrent Auto Precharge option is supported

• Data Mask (DM) for masking write data

• Programmable Burst lengths: 4, 8

• Programmable /CAS Latency (CL): 3, 4, 5

• Posted /CAS Additive Latency (AL): 0, 1, 2, 3, and 4

• WRITE latency = READ latency-1 tCK

• READ burst interrupt supported by another READ;

• Adjustable data-output drive strength

• Serial Presence Detect (SPD) with EEPROM

• ECC, 1-bit error detection and correction

• Gold Edge contacts

• RoHS Compliant, lead free

edge aligned with data for READs and center-aligned

with data for WRITES; DLL to align DQ and DQS

transitions with CK

operation

WRITE burst interrupt supported by another WRITE

Related parts for SL72P4M128M8M-B05AYU

SL72P4M128M8M-B05AYU Summary of contents

Page 1

... X 72 Bit (1GB) 240-Pin DDR2 Registered RDIMM ECC (PC2-3200) Very Low Profile (VLP) 1 Rank x 4; RoHS Compliant GENERAL DESCRIPTION The SL72P4M128M8M-B05AY(W 128M x 72 bit (1GB) 240-pin Double Data Rate 2 (DDR2) Registered Dual In-line Memory Module (RDIMM) with ECC. The module consists of eighteen CMOS 32M x 4 bit x 4 bank DDR2 SDRAMs in lead-free BGA packages mounted in 1 rank on a 240-pin glass epoxy substrate ...

Page 2

... SL72P4M128M8M-B05AY(W)U DIMENSIONS (Board No. 1235) Units are in inches (millimeters). All dimensions are typical unless otherwise specified. 0.157 (4.00) 0.394 2.48 (63.0) (10.0) 0.197 (5.0) 0.039 (1.0) 5.250 (133.35) EEPROM PLL Register 2.165 (55.0) 4.840 (123.0) 0.031 (0.80) 0.030 (0.76) R Document Part Number 61000-02973-106 July 2007 Page 2 240-PIN RDIMM 0 ...

Page 3

... SL72P4M128M8M-B05AY(W)U PIN CONFIGURATION (* = Not Used Active Low; Bold Line = Key) 240-Pin DIMM Front Pinout Pin Symbol Pin Symbol Pin Symbol Pin 1 VREF 31 DQ19 61 2 VSS 32 VSS 62 3 DQ0 33 DQ24 63 4 DQ1 34 DQ25 64 5 VSS 35 VSS 65 6 /DQS0 36 /DQS3 66 7 DQS0 37 DQS3 ...

Page 4

... SL72P4M128M8M-B05AY(W)U PIN CONFIGURATION continued (* = Not Used Active Low) Pin Functions Symbol CK0, /CK0 CKE0 /S0 ODT0 /RAS, /CAS, /WE BA0-BA1 A0-A13 DQ0-DQ63 CB0-CB7 DQS0-DQS17, /DQS0-/DQS17 SCL SA0-SA2 SDA /RESET NC RFU VDDQ VDD VSS VREF VDDSPD PAR-IN ERR-OUT Type Function Input Clock Input ...

Page 5

... SL72P4M128M8M-B05AY(W)U FUNCTIONAL BLOCK DIAGRAM VSS /RS0 DQS0 /DQS0 /DQS9 NU, DM, /CS DQS /DQS RDQS /RDQS DQ0 DQ0 DDR2 DQ1 DQ1 SDRAM DQ2 DQ2 U1 DQ3 DQ3 DQS1 DQS10 /DQS1 /DQS10 DM, NU, /CS DQS /DQS RDQS /RDQS DQ4 DQ0 DDR2 DQ5 DQ1 SDRAM DQ6 DQ2 ...

Page 6

... SL72P4M128M8M-B05AY(W)U SERIAL PRESENCE DETECT INFORMATION 2 C; Current sink capability of SDA driver ≤3mA; Maximum clock frequency: 100 KHz Serial PD Interface Protocol: I Byte Description 0 Number of SPD Bytes Used by STEC 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly ...

Page 7

... SL72P4M128M8M-B05AY(W)U SERIAL PRESENCE DETECT INFORMATION Byte Description 45 SDRAM Device Max Read Data Hold Skew Factor, tQHS 46 PLL Relock Time 47-61 Reserved 62 SPD Revision 63 Checksum For Bytes 0-62 64 Manufacturer’s JEDEC ID Code STEC 65 Man. JEDEC ID code (continued) 66-71 Reserved 72 Manufacturing Location 73-90 Module Part Number (ASCII) ...

Page 8

... SL72P4M128M8M-B05AY(W)U ABSOLUTE MAXIMUM DC RATINGS Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional Operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods may affect device reliability. Symbol Parameter VDD VDD Supply Voltage Relative to VSS ...

Page 9

... SL72P4M128M8M-B05AY(W)U INPUT ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS Input DC Logic Levels All voltages referenced to VSS. Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input AC Logic Levels All voltages referenced to VSS. Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage IDD SPECIFICATIONS AND CONDITIONS IDD specifications are tested after the device is properly initialized. 0° ...

Page 10

... SL72P4M128M8M-B05AY(W)U DDR2 IDD Specifications and Conditions Notes: 1–5. Values shown for DDR2 SDRAM components only. Symbol—Parameter/Condition IDD0—Operating one bank active-precharge current; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING ...

Page 11

... SL72P4M128M8M-B05AY(W)U CAPACITANCE Vdd = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VREF = VSS 100 MHz, 0°C ≤ ≤ ≤ ≤ ≤ TOPR ≤ ≤ ≤ ≤ ≤ +55°C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 0.1V; DM input is grouped with I/O pins because DM and the I/O pins are matched in loading. ...

Page 12

... SL72P4M128M8M-B05AY(W)U AC OPERATING CONDITIONS AC Characteristics Parameter Command and Address Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input setup time Address and control input hold time ...

Page 13

... SL72P4M128M8M-B05AY(W)U NOTES 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: VTT=VDDQ/2 25 Ω ...

Page 14

... SL72P4M128M8M-B05AY(W)U NOTES (continued) 21. READS AND WRITES WITH AUTO PRECHARGE are allowed to be issued before tRAS (MIN) is satisfied since tRAS lockout feature is supported in DDR2 SDRAM devices. 22. VIL/VIH DDR2 overshoot/undershoot. REFER TO the 256Mb, 512Mb, or 1Gb DDR2 SDRAM data sheet for more detail. 23. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period ...

Page 15

... SL72P4M128M8M-B05AY(W)U REGISTER ELECTRICAL CHARACTERISTICS 0°C≤TOPR≤+70°C; VDD=VDDQ=+2.5V ±0.2V; Unless otherwise stated Symbol Parameters Conditions VIK II = -18mA VOH IOH = -100µA IOH = -16mA VOL IOL = 100µA IOL = 16mA II All Inputs VI = VDD or GND 0.01 IDD Standby (Static) /RESET = GND ...

Page 16

... SL72P4M128M8M-B05AY(W)U PLL CLOCK DRIVER ELECTRICAL CHARACTERISTICS 0°C≤TOPR≤+70°C; AVDDQ=VDDQ=+1.8V ±0.1V; Unless otherwise stated Symbol Parameters IIH Input High Current (CLK_INT, CLK_INC) IIL Input Low Current (OE, OS, FB_INT, FB_INC) IODL Output Disabled Low Current IDD1.8 Operating Supply Current IDDLD ...

Page 17

... SL72P4M128M8M-B05AY(W)U REVISION HISTORY Rev. Change Description from Previous Revision -101 07/16/2004. Initial release. -102 08/06/2004. Board height updated from 18mm to 18.3mm. -103 01/27/2005. Preliminary notice removed. P/N changed to -D05AYU. -104 04/18/2005. P/N changed to -B05AYU from -D05AYU. tCK(5) speeds added in SPD and AC Characteristics. ...

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