EP1K10TI144-2 Altera, EP1K10TI144-2 Datasheet - Page 8

• Manufacturer Part Number: EP1K10TI144-2
• Manufacturer: Altera

Specifications of EP1K10TI144-2

• Family Name: ACEX™ 1K
• Number Of Usable Gates: 10000
• Number Of Logic Blocks/elements: 576
• # I/os (max): 92
• Frequency (max): 200MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 576
• Ram Bits: 12288
• Device System Gates: 56000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

ACEX 1K Programmable Logic Device Family Data Sheet
Figure 1. ACEX 1K Device Block Diagram
8
Row
Interconnect
I/O Element
(IOE)
Column
Interconnect
Logic
Array
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
ACEX 1K devices provide six dedicated inputs that drive the flipflops’
control inputs and ensure the efficient distribution of high-speed, low-
skew (less than 1.0 ns) control signals. These signals use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global signals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generated asynchronous clear signal that clears many registers in the
device.
IOE
IOE
IOE
IOE
IOE
IOE
Embedded Array Block (EAB)
IOE
IOE
Embedded Array
EAB
EAB
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Altera Corporation
IOE
IOE
IOE
IOE
Logic Array
Block (LAB)
Logic Array
Local Interconnect
Logic Element (LE)