EP1K10TI144-2 Altera, EP1K10TI144-2 Datasheet - Page 33

• Manufacturer Part Number: EP1K10TI144-2
• Manufacturer: Altera

Specifications of EP1K10TI144-2

• Family Name: ACEX™ 1K
• Number Of Usable Gates: 10000
• Number Of Logic Blocks/elements: 576
• # I/os (max): 92
• Frequency (max): 200MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 576
• Ram Bits: 12288
• Device System Gates: 56000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
Figure 16. ACEX 1K Row-to-IOE Connections
Note:
(1)
The values for m and n are shown in
Row FastTrack
Interconnect
n
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row
channels. The signal is accessible by all LEs within that row. When an IOE
is used as an output, the signal is driven by a multiplexer that selects a
signal from the row channels. Up to eight IOEs connect to each side of
each row channel (see
Table 8
EP1K10
EP1K30
EP1K50
EP1K100
Table 8. ACEX 1K Row-to-IOE Interconnect Resources
Device
lists the ACEX 1K row-to-IOE interconnect resources.
Table
Each IOE can drive two
row channels.
n
n
m
m
8.
Note (1)
ACEX 1K Programmable Logic Device Family Data Sheet
Figure
Channels per Row (n)
m-to-1 multiplexer.
Each IOE is driven by an
16).
144
216
216
312
IOE8
IOE1
Row Channels per Pin (m)
18
27
27
39
33
13