MT48LC4M32LFF5-10:G TR Micron Technology Inc, MT48LC4M32LFF5-10:G TR Datasheet - Page 58

• Manufacturer Part Number: MT48LC4M32LFF5-10:G TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48LC4M32LFF5-10:G TR

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 22/8/7ns
• Maximum Clock Rate: 100MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 110mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Timing Diagrams
Figure 38:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN
DQML, DQMU
COMMAND 1,2
A0–A9, A11
BA0, BA1
CKE
A10
CLK
DQ
5
Initialize and Load Mode Register
T = 100µs
Power-up:
V
CLK stable
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Notes:
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CMS
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CKS
T0
NOP
1. The two AUTO REFRESH commands at T9 and T19 may be applied either before LOAD
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH
3. The LOAD MODE REGISTER both for mode register and for extended mode register, and
4. Optional REFRESH command.
5. Although not required, to prevent bus contention, it is suggested to keep DQM HIGH dur-
t
High-Z
CMH
t
CKH
t
CK
MODE REGISTER (LMR) command.
command, ACT = ACTIVE command, RA = row address, and BA = bank address.
two AUTO REFRESH commands can be in any order. However, all must occur prior to an
ACTIVE command.
ing the initialization sequence. See Table 17 on page 52.
ALL BANKS
t
AS
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T1
t AH
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Load Extended
Mode Register
t AS
t AS t AH
BA0 = L,
BA1 = H
LMR 3
CODE
CODE
T3
t AH
t
MRD
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Load Mode
58
Register
BA0 = L,
BA1 = L
CODE
CODE
LMR 3
T5
t
MRD
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
ALL BANKS
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T7
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AH
128Mb: x16, x32 Mobile SDRAM
t
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AR
T9
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©2001 Micron Technology, Inc. All rights reserved.
AR 4
T19
Timing Diagrams
t
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DON’T CARE
ACT
T29
RA
RA
BA