MT48LC4M32LFF5-10:G TR Micron Technology Inc, MT48LC4M32LFF5-10:G TR Datasheet - Page 47
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MT48LC4M32LFF5-10:G TR
Manufacturer Part Number
MT48LC4M32LFF5-10:G TR
Description
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48LC4M32LFF5-10G_TR.pdf
(79 pages)
Specifications of MT48LC4M32LFF5-10:G TR
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
22/8/7ns
Maximum Clock Rate
100MHz
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
110mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
9. Burst in bank n continues as initiated.
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
burst has been interrupted by bank m’s burst.
charge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 14 on
page 28).
charge), the WRITE to bank m will interrupt the READ on bank n when registered (see
Figure 16 and Figure 17 on page 30). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
charge), the READ to bank m will interrupt the WRITE on bank n when registered (see
Figure 24 on page 36) with the data-out appearing CL later. The last valid WRITE to bank n
will be data-in registered 1 clock prior to the READ to bank m.
charge), the WRITE to bank will interrupt the WRITE on bank n when registered (see
Figure 22 on page 35). The last valid WRITE to bank n will be data-in registered 1 clock prior
to the READ to bank m.
the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n
will begin when the READ to bank m is registered (see Figure 31 on page 41).
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used 2 clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to
bank n will begin when the WRITE to bank m is registered (see Figure 32 on page 41).
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The PRECHARGE to bank n will begin after
begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in
registered 1 clock prior to the READ to bank m (see Figure 33 on page 42).
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after
istered. The last valid WRITE to bank n will be data registered 1 clock to the WRITE to bank
m (see Figure 34 on page 42).
t
WR is met, where
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR begins when the WRITE to bank m is reg-
128Mb: x16, x32 Mobile SDRAM
t
WR is met, where
©2001 Micron Technology, Inc. All rights reserved.
t
READs
WR