LFXP10E-3FN256C Lattice, LFXP10E-3FN256C Datasheet - Page 215
LFXP10E-3FN256C
Manufacturer Part Number
LFXP10E-3FN256C
Description
IC FPGA 9.7KLUTS 188I/O 256-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP10E-3FN256C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 9-60. PFU-based Distributed ROM (Sync_ROM) for LatticeECP/EC and LatticeXP Devices
Ports such as Out Clock (OutClock) and Out Clock Enable (OutClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
The various ports and their definitions for the memory are included in Table 9-16. The table lists the corresponding
ports for the module generated by IPexpress and for the primitive.
Table 9-16. PFU-based Distributed ROM Port Definitions
Users have the option of enabling the output registers for Distributed ROM (Distributed_ROM). Figures 8-43 and 8-
44 show the internal timing waveforms for the Distributed ROM with these options.
Figure 9-61. PFU Based ROM Timing Waveform – without Output Registers
Address
OutClock
OutClockEn
Reset
Q
Port Name in Generated
Module
Address
Q
AD[3:0]
—
—
—
DO
Invalid Data
Port Name in the EBR
t
SUADDR_PFU
Block Primitive
AD[3:0]
Add_0
t
HADDR_PFU
t
CORAM_PFU
9-50
PFU
Address
Out Clock
Out Clock Enable
Reset
Data Out
Data_0
Add_1
Description
LatticeECP/EC and LatticeXP Devices
DO
Data_1
Add_2
—
Rising Clock Edge
Active High
Active High
—
Memory Usage Guide
Active State
Data_2
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