LFXP6C-3TN144I Lattice, LFXP6C-3TN144I Datasheet - Page 272
LFXP6C-3TN144I
Manufacturer Part Number
LFXP6C-3TN144I
Description
IC FPGA 5.8KLUTS 100I/O 144-TQFP
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP6C-3TN144I
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-3TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
DCS MODE = NEG
At the falling edge (NEG) of SEL, the DCSOUT changes from CLK0 to CLK1.
DCS MODE = HIGH_LOW
SEL is active high (HIGH) to select CLK1, and the disabled output is LOW.
DCS MODE = LOW_LOW
SEL is active low (LOW) to select CLK0, and the disabled output is LOW.
DCS MODE = HIGH_HIGH
SEL is active high (HIGH) to select CLK1, and the disabled output is HIGH.
DCS MODE = LOW_HIGH
SEL is active low (LOW) to select CLK0, and the disabled output is HIGH.
DCSOUT
SEL
CLK1
DCSOUT
CLK1
SEL
CLK0
- Switch low at CLK1 falling edge.
- If SEL is low, output stays low at on
CLK1 rising edge. SEL must not
change during setup prior to rising clock.
DCS MODE = HIGH_LOW
SEL Falling edge:
- Wait for CLK1 falling edge,
- Switch output at CLK0 falling edge
latch output & remain low
DCS MODE = NEG
11-16
DCSOUT
sysCLOCK PLL Design and Usage Guide
SEL
CLK0
- Switch low at CLK0 falling edge.
- If SEL is high, output stays low at
on CLK0 rising edge.
SEL Rising edge:
- Wait for CLK0 falling edge,
- Switch output at CLK1 falling edge
DCS MODE = LOW_LOW
latch output & remain low
LatticeECP/EC and LatticeXP
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