NOII5FM1300A-QDC ON Semiconductor, NOII5FM1300A-QDC Datasheet - Page 21

• Manufacturer Part Number: NOII5FM1300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOII5FM1300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 20
Global Shutter: Single Slope Integration
SS_START and SS_STOP must change on the falling edge of
the SYS_CLOCK (Tsetup and Thold > 7.5 ns). Make certain that
the pulse width of both signals is a minimum of 1 SYS_CLOCK
cycle. As long as SS_START or SS_STOP are asserted, the
sequencer stays in a suspended state (see
T
INT_TIME register is reached. The integration timer is clocked
by the granulated SS-sequencer clock.
T
SS-sequencer clock period.
1
2
- Time counted by the integration timer until the value of
- TIME_OUT signal stays high for one granulated
shows a recommended schematic for generating the basic signals and to avoid any timing problems.
Figure 21. Relative Timing of 5-Sequencer Control Signal
Figure 20. .Recommended Schematic for Basic Signals
SYS_CLOCK_N
Figure 22. Global Shutter: Single Slope Integration
Figure
Rev. 9 | www.onsemi.com | Page 21 of 34
22).
FF
T
signal to trigger the SS_STOP pin (or use an external counter to
trigger SS_STOP); you cannot tie both signals together.
T
signals to reset the image core and start integration. This takes
four granulated SS-sequencer clock periods. The integration
time counter starts counting at the first rising edge after the falling
edge of SS_START.
T
It takes two granulated SS-sequencer clock periods.
T
int
3
4
5
- The SS-sequencer puts the image core in a readable state.
- There are no constraints for this time. Use the TIME_OUT
- During this time, the SS-sequencer applies the control
- The ’real’ integration or exposure time.
SS_START
SS_STOP
Y_CLOCK
Y_START
X_LOAD
SYS_CLOCK
NOII5SM1300A