NOII5FM1300A-QDC ON Semiconductor, NOII5FM1300A-QDC Datasheet
NOII5FM1300A-QDC
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NOII5FM1300A-QDC Summary of contents
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... See Ordering Code Information on page 33 for more information. Marketing Part Number NOII5SM1300A-QDC NOII5SM1300A-QWC NOII5SC1300A-QDC NOII5FM1300A-QDC Semiconductor Components Industries, LLC, 2011 © June, 2011 - Rev. 9 IBIS5 1.3 Megapixel CMOS Image Sensor Description The IBIS5-1300 is a solid state CMOS image sensor that integrates the functionality of complete analog image acquisition, digitizer, and digital signal processing system on a single chip. This 1.3-mega pixel (1280 × ...
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Contents Features .................................................................................. 1 Applications ........................................................................... 1 Description ............................................................................. 1 Ordering Information ............................................................. 1 Specifications ........................................................................ 3 Key Specifications ............................................................ 3 Electrical Specifications .................................................... 4 Architecture and Operation .................................................. 5 Floor Plan ......................................................................... 5 Pixel .................................................................................. 6 Image Core Operation ...
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... Operating ratings are conditions in which operation of the device is intended to be functional Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625-A. Refer to Application Note AN52561. 4. The IBIS5-1300 complies with JESD22-A114 HBM Class 0 and JESD22-C101 Class recommended that extreme care be taken while handling these devices to avoid damages due to ESD event ...
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Electrical Specifications Recommended Operating Conditions Table 5. Recommended Operating Conditions Parameter Description VDDH Voltage on HOLD switches. VDDR_LEFT Highest reset voltage. VDDC Pixel core voltage. VDDA Analog supply voltage of the image core. VDDD Digital supply voltage of the image ...
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Architecture and Operation This section presents detailed information about the most important sensor blocks Y-left addressing Floor Plan Figure 2 shows the architecture of the IBIS5-1300 image sensor. It consists basically of a pixel array, one X- and two Y-addressing ...
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Pixel A description of the pixel architecture and the color filter array follows. Architecture The pixel architecture used in the IBIS5-1300 is a 4-transistor pixel as shown in Figure 3. Implement the pixel using the high fill factor technique. The ...
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... The curve is measured directly on the pixels. It includes effects of non-sensitive areas in the pixel, for example, interconnection lines. The sensor is light sensitive between 400 and 1000 nm. The peak QE × 30%, approximately around 650 nm. In view of a fill factor of 40%, the QE is thus close to 75% between 500 and 700 nm. The NOII5FM1300A has superior response in the NIR region (700-900 nm). ...
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... NOII5FM1300A: The NOII5FM1300A is processed on a thicker epitaxial silicon featuring higher sensitivity in the NIR (Near Infra Red) wavelengths (700–900 nm). The spectral response curves, highlighting the difference between IBIS5-1300 using the standard process and thicker epitaxial layer process are shown in Figure 6 NOII5FM1300A sensor has a significant sensitivity advantage in the NIR domain ...
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Image Core Operation Image Core Operation and Signalling Figure functional representation of the image core without sub-sampling and column/row swapping circuits. Most of the signals involved are not available from the outside because they are generated by ...
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Global Shutter Supply Considerations The recommended supply voltage settings listed in used when the sensor is in global shutter mode only. Table 8. Global Shutter Recommended Supply Settings Parameter Description VDDH Voltage on HOLD switches. VDDR_LEFT Highest reset voltage. VDDC ...
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X-Addressing Because of the high pixel rate, the X-shift register selects two columns at a time for readout runs at half the system clock speed. All even columns are connected to bus A; all odd columns to bus ...
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Output Amplifier Architecture and Settings The output amplifier stage is user programmable for gain and offset level. Gain is controlled by 4-bit wide word; offset by a 7-bit wide word. Gain settings are on an exponential scale. Offset is controlled ...
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Analog-to-Digital Converter The IBIS5-1300 has a 10-bit flash analog digital converter running nominally at 40 Msamples/s. The ADC is electrically separated from the image sensor. Tie the input of the ADC (ADC_IN; pin 69) externally to the output (PXL_OUT1; pin ...
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Nonlinear and Linear Conversion Mode—’gamma’ Correction Figure 15 shows the ADC transfer characteristic. The nonlinear (exponential) ADC conversion is intended for gamma-correction of the images. It increases contrast in dark areas and reduces contrast in bright areas. The non-linear transfer ...
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Electronic Shutter Types The IBIS5-1300 has two shutter types: a rolling (curtain) shutter and a global shutter. Rolling (Curtain) Shutter The name is due to the fact that the effect is similar to a curtain shutter of a SLR film ...
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Table 15. Internal Registers Register Bit Name 0 (0000) 11:0 SEQUENCER register 0 SHUTTER_TYPE 1 FRAME_CAL_MODE 2 LINE_CAL_MODE 3 CONT_CHARGE 4 GRAN_X_SEQ_LSB 5 GRAN_X_SEQ_MSB 6 GRAN_SS_SEQ_LSB 7 GRAN_SS_SEQ_MSB 8 KNEEPOINT_LSB 9 KNEEPOINT_MSB 10 KNEEPOINT_ENABLE 11 VDDR_RIGHT_EXT 1 (0001) 11:0 NROF_PIXELS ...
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Table 15. Internal Registers (continued) Register Bit Name 9 (1001) 6:0 DACRAW_REG 10 (1010) 6:0 DACFINE_REG 11 (1011) 2:0 ADC register 0 TRISTATE_OUT 1 GAMMA 2 BIT_INV 12 (1100) Reserved 13 (1101) Reserved 14 (1110) Reserved 15 (1111) Reserved Detailed ...
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Bits KNEE_POINT_MSB and KNEE_POINT_LSB select the on chip-generated pixel reset voltage. Bit KNEE_POINT_ENABLE set to ’1’ switches control to the right side of the image core so the pixel reset voltage (VDDR_RIGHT), selected by bits KNEE_POINT_MSB/LSB, is used. Use bit ...
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X_REG Register (10:0) The X_REG register determines the start position of the window in the X-direction. In this direction, there are 640 possible starting positions (two pixels are addressed at the same time in one clock cycle). If sub sampling ...
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Timing Diagrams Frame Rate The pixel rate for this sensor is high enough to support a frame rate of greater than 100 Hz for a window size of 640 × 480 pixels (VGA format). Considering a row blanking time of ...
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Figure 20 shows a recommended schematic for generating the basic signals and to avoid any timing problems. Figure 20. .Recommended Schematic for Basic Signals Figure 21. Relative Timing of 5-Sequencer Control Signal Global Shutter: Single Slope Integration SS_START and SS_STOP ...
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Global Shutter: Pixel Readout Basic Operation Y_START and Y_CLOCK must change on the falling edge of the SYS_CLOCK (Tsetup and Thold > 7.5 ns). Make certain that the pulse width is a minimum of one clock cycle for Y_CLOCK and ...
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Global Shutter: Multiple Slope Integration Use up to four different pixel reset voltages during multiple slope operation in synchronous shutter mode. This is done by uploading new values KNEEPOINT_MSB/LSB/ENABLE before a new SS_START pulse is applied. Set bit KNEEPOINT_ENABLE high ...
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Rolling Shutter Operation The integration of the light in the image sensor is done during readout of the other lines. The only difference with synchronous shutter is that the TIME_OUT pin is used to indicate when the Y_SYNC pulse for ...
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Windowing in Y-Direction Reapply the Y_START pulse after loading a new Y-pointer value into the YL_REG and YR_REG registers to load a new Y-pointer into the Y-shift-register. Every time a Y_START pulse appears, a frame calibration of the output amplifier ...
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Package Information Pin List The IBIS5-1300 image sensor has 84 pins and is packaged in a leadless ceramic carrier (LCC) package. their functions. [8, 9, 10] Table 26. Pin List Pin Pin Name Pin Type 1 P_DATA<8> Input 2 P_WR ...
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Table 26. Pin List (continued) Pin Pin Name Pin Type 29 PXL_OUT2 Output 30 AMP_CMD Input 31 COL_CMD Input 32 PC_CMD Input 33 VDDD Supply 34 GNDD Ground 35 GNDA Ground 36 VDDA Supply 37 VDDC Supply ...
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Table 26. Pin List (continued) Pin Pin Name Pin Type 65 ADC_OUT<3> Output 66 ADC_OUT<2> Output 67 ADC_OUT<1> Output 68 ADC_OUT<0> Output 69 ADC_IN Input 70 ADC_CMD Input 71 ADC_VDDD Supply 72 ADC_GNDA Ground 73 ADC_GNDD Ground ...
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Pad Position and Packaging Bare Die The IBIS5-1300 image sensor has 84 pins, 21 pins on every edge. The die size from pad-edge to pad-edge (without scribe-line) is: 10156.5 µm (x) by 9297.25 µm (y). Scribe lines take about 100 ...
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Package Drawing with Glass Rev www.onsemi.com | Page NOII5SM1300A 001-07589 *A ...
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Table 27. Side View Dimensions (see Dimension Description A Glass (thickness) - mono B Cavity (depth) C Die - Si (thickness) - mono D Bottom layer (thickness) E Die attach-bondline (thickness) F Glass attach-bondline (thickness) G Imager to lid-outer surface ...
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... ON Semiconductor will either replace the product or give credit for the product. Return Material Authorization (RMA) ON Semiconductor packages all of its image sensor products in a clean room environment under strict handling procedures and ships all ...
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... M 1300 The ON Semiconductor Video Capture software (provided in the CD with reference schematics) is compatible with Windows-XP operating system and allows to grab live images from the sensor, store the images in different formats for analysis and test different functional modes of the sensor Figure 32. The IBIS5-1300 Demo Kit Rev ...
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