DP83848IVV National Semiconductor, DP83848IVV Datasheet - Page 67

• Manufacturer Part Number: DP83848IVV
• Manufacturer: National Semiconductor

Specifications of DP83848IVV

• Lead Free Status / Rohs Status: Compliant

8.2.5 100 Mb/s MII Receive Timing
Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered
clocks. Minimum high and low times will not be violated.
8.2.6 100BASE-TX Transmit Packet Latency Timing
Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after
the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100
Mb/s mode.
T2.5.1
T2.5.2
Parameter
T2.6.1
Parameter
PMD Output Pair
RX_CLK
RXD[3:0]
RX_DV
RX_ER
RX_CLK High/Low Time
RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode
TX_CLK to PMD Output Pair
Latency
TX_CLK
TX_EN
TXD
Description
T2.5.2
Description
T2.5.1
IDLE
100 Mb/s Normal mode
T2.6.1
67
Valid Data
100 Mb/s Normal mode
Notes
(J/K)
Notes
T2.5.1
DATA
Min
Min
16
10
Typ
6
Typ
20
Max
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Max
24
30
Units
bits
Units
ns
ns