L80227-LEADFREE LSI, L80227-LEADFREE Datasheet - Page 69

• Manufacturer Part Number: L80227-LEADFREE
• Manufacturer: LSI

Specifications of L80227-LEADFREE

• Lead Free Status / Rohs Status: Compliant

4.3
4.3.1
COLTST
RST
15
7
Registers
Control Register (Register 0)
LPBK
14
6
This section contains a description of each of the bits in each register.
The default value for this register is 0x3400.
RST
LPBK
SPEED
ANEG_EN
Registers
SPEED
13
Reset
Bit
1
0
Loopback Enable
Bit
1
0
Speed Select
Bit
1
0
1. The SPEED bit is effective only when AutoNegotiation is off
AutoNegotiation Enable
Bit
1
0
ANEG_EN
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
1
12
Meaning
Reset. The bit is bit self-clearing in less than or equal to
200 s after reset finishes.
Normal (Default)
Meaning
Loopback mode enabled
Normal (Default)
Meaning
100 Mbit/s (100BASE-TX) (default)
10 Mbit/s (10BASE-T)
Meaning
1 = AutoNegotiation enabled (default)
0 = Disabled
Reserved
PDN
11
MII_DIS
10
ANEG_RST
9
R/WSC 15
DPLX
R/W 14
R/W 13
R/W 12
8
0
4-5