L80227-LEADFREE LSI, L80227-LEADFREE Datasheet - Page 51

• Manufacturer Part Number: L80227-LEADFREE
• Manufacturer: LSI

Specifications of L80227-LEADFREE

• Lead Free Status / Rohs Status: Compliant

2.6 Full-/Half-Duplex Mode
Figure 2.8
585 mV sin (2
0
225
The TP receiver senses missing data transitions in order to detect the
receive SOI pulse. Once the SOI pulse is detected, data reception is
ended and the CRS and RX_DV pins are deasserted.
Half-Duplex mode is the CSMA/CD operation defined in IEEE 802.3. It
allows transmission or reception, but not both at the same time. Full-
Duplex operation is a mode that allows simultaneous transmission and
reception. Full duplex in the 10 Mbits/s mode is identical to operation in
the 100 Mbits/s mode.
The device can be forced into either the Full- or Half-Duplex mode, or
the device can use AutoNegotiation to autoselect Full-/Half-Duplex
operation. When a channel is placed in Full-Duplex mode:
Full-/Half-Duplex Mode
t
The collision function is disabled, and
TX_EN to CRS loopback is disabled
t
0.25 BT and
585 mV
2.5 BT
3.1 V
SOI Output Voltage Template (10 Mbits/s)
0 BT
(t/1 BT))
3.1 V
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
0.25 BT
2.5 BT
0.5 V/ns
2.25 BT
4.5 BT
4.5 BT
6.0 BT
45.0 BT
+ 50 mV
50 mV
2-33