AM79C971AKC\WQOCML AMD (ADVANCED MICRO DEVICES), AM79C971AKC\WQOCML Datasheet - Page 139

• Manufacturer Part Number: AM79C971AKC\WQOCML
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C971AKC\WQOCML

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Commercial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / Rohs Status: Not Compliant

CSR58: Software Style
This register is an alias of the location BCR20. Accesses
to and from this register are equivalent to accesses to
BCR20.
Bit
31-16 RES
15-11 RES
10
APERREN
Name
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
that since the advanced parity er-
ror handling uses an additional bit
in the descriptor, SWSTYLE (bits
7-0 of this register) must be set to
2 or 3 to program the Am79C971
controller to use 32-bit software
structures.
If the user does not use the stan-
dard
(standard implies use of an initial-
ization block in memory and set-
ting the INIT bit of CSR0), but
instead, chooses to write directly
to each of the registers that are
involved in the INIT operation,
then it is imperative that the user
also writes all zeros to CSR49 as
part of the alternative initialization
sequence.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur when
the Am79C971 controller is the
target of the transfer.
Read anytime, write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
Description
initialization
P R E L I M I N A R Y
procedure
Am79C971
9
8
RES
SSIZE32
Reserved locations. Written as
zeros and read as undefined.
Software Size 32 bits. When set,
this
Am79C971 controller utilizes 32-
bit software structures for the ini-
tialization block and the transmit
and receive descriptor entries.
When cleared, this bit indicates
that the Am79C971 controller uti-
lizes 16-bit software structures for
the initialization block and the
transmit and receive descriptor
entries.
Am79C971 controller is back-
wards
Am7990 LANCE and Am79C960
PCnet-ISA controllers.
The value of SSIZE32 is deter-
mined by the Am79C971 control-
ler according to the setting of the
Software Style (SWSTYLE, bits
7-0 of this register).
Read
SSIZE32 is read only; write oper-
ations will be ignored. SSIZE32
will be cleared after H_RESET
(since SWSTYLE defaults to 0)
and is not affected by S_RESET
or STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32-bit address
bus during master accesses initi-
ated by the Am79C971 controller.
This action is required, since the
16-bit software structures speci-
fied by the SSIZE32 = 0 setting
will yield only 24 bits of address
for the Am79C971 controller bus
master accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the Am79C971 controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the Am79C971
controller for performing master
accesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 ad-
bit
compatible
In
accessible
indicates
this
mode,
with
that
always.
139
the
the
the