AM79C971AKC\WQOCML AMD (ADVANCED MICRO DEVICES), AM79C971AKC\WQOCML Datasheet
AM79C971AKC\WQOCML
Specifications of AM79C971AKC\WQOCML
Related parts for AM79C971AKC\WQOCML
AM79C971AKC\WQOCML Summary of contents
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Am79C971 PCnet™-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus DISTINCTIVE CHARACTERISTICS Single-chip Fast Ethernet controller for the Peripheral Component Interconnect (PCI) local bus — 32-bit glueless PCI host interface — Supports PCI clock frequency from DC to ...
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Supports Megabyte (Mbyte) optional Boot PROM and Flash for diskless node application Look-Ahead Packet Processing (LAPP) data handling technique reduces system overhead by allowing protocol analysis to begin before the end of a receive frame Includes Programmable ...
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In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, receive po- larity, link integrity, activity, link active, address match, full-duplex, MII select, 100 Mbps, or jabber status. The Am79C971 controller also provides an EADI to allow ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79C971 K\V Valid Combinations Am79C971 ALTERNATE PACKAGING OPTION ...
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BLOCK DIAGRAM CLK RST AD[31:00] C/BE[3:0] PAR FRAME TRDY PCI Bus IRDY Interface Unit STOP IDSEL DEVSEL REQ GNT PERR SERR INTA SLEEP Buffer Management Unit TCK JTAG TMS Port TDI Control TDO EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS ERAMCS AS_EBOE EBWE ...
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TABLE OF CONTENTS AM79C971 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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TX_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SWITCHING WAVEFORMS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . .226 SWITCHING WAVEFORMS: EXTERNAL ADDRESS DETECTION INTERFACE ...
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RELATED AMD PRODUCTS Part No. Description Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am79865 100 Mbps Physical Data Transmitter (PDT) ...
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CONNECTION DIAGRAM (PQR160) IDSEL 1 VDD 2 AD23 3 AD22 4 VSS 5 AD21 6 AD20 7 VDD_PCI 8 AD19 9 AD18 10 VSSB 11 AD17 12 AD16 13 C/BE2 14 15 FRAME IRDY 16 TRDY 17 DEVSEL 18 19 ...
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CONNECTION DIAGRAM (PQL176 IDSEL 4 VDD 5 AD23 6 AD22 7 VSS 8 AD21 9 AD20 10 VDD_PCI 11 AD19 12 AD18 13 VSSB 14 AD17 15 AD16 16 C/BE2 17 FRAME 18 IRDY 19 ...
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PIN DESIGNATIONS (PQR160) Listed By Pin Number Pin Pin Pin Pin No. Name No. Name 1 IDSEL 41 AD5 2 VDD 42 AD4 3 AD23 43 AD3 4 AD22 44 AD2 5 VSS 45 VDD_PCI 6 AD21 46 AD1 7 ...
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PIN DESIGNATIONS (PQL176) Listed By Pin Number Pin Pin Pin Pin No. Name No. Name IDSEL 47 AD5 4 VDD 48 AD4 5 AD23 49 AD3 6 AD22 50 AD2 7 ...
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PIN DESIGNATIONS (PQR160, PQL176) Listed By Group Pin Name Pin Function PCI Bus Interface AD[31:0] Address/Data Bus C/BE[3:0] Bus Command/Byte Enable CLK Bus Clock DEVSEL Device Select FRAME Cycle Frame GNT Bus Grant IDSEL Initialization Device Select INTA Interrupt IRDY ...
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PIN DESIGNATIONS Listed By Group Pin Name Pin Function Media Independent Interface (MII) COL Collision CRS Carrier Sense MDC Management Data Clock MDIO Management Data I/O RX_CLK Receive Clock RXD[3:0] Receive Data RX_DV Receive Data Valid RX_ER Receive Error TX_CLK ...
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PIN DESIGNATIONS Listed By Group Pin Name Pin Function Power Supplies AVDDB Analog I/O Buffer Power AVSSB Analog I/O Buffer Ground VDD_PLL Analog PLL Power VSS_PLL Analog PLL Ground VDD Digital Power VSS Digital Ground VDDB I/O Buffer Power VSSB ...
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PIN DESCRIPTIONS PCI Interface AD[31:0] Address and Data Address and data are multiplexed on the same bus in- terface pins. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During the subsequent clocks, AD[31:0] contain ...
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INTA Interrupt Request An attention signal which indicates that one or more of the following status flags is set: BABL, EXDINT, IDON, JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, SLPINT, TINT, TXSTRT, UINT, MCCIINT, MC- CINT, MPDTINT, MAPINT, MREINT, ...
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PERR Parity Error During any slave write transaction and any master read transaction, the Am79C971 controller asserts PERR when it detects a data parity error and reporting of the error is enabled by setting PERREN (PCI Command register, bit 6) ...
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HIGH, the output is a totem pole driver. Note: The LED1 pin is multiplexed with the EESK and SFBD pins. The LED1 pin is also used during EEPROM Auto- Detection to determine whether or not ...
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Note: When the Am79C971 controller is in coma mode, there is an internal 22 k resistor from XTAL1 to ground external source drives XTAL1, some power consumption will ...
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EBDA[15:8] Expansion Bus Data/Address [15:8] When ERAMCS is asserted, EBDA[15:8] contain the data bits [15:8] for SRAM accesses. When EROMCS is asserted low, EBDA[15:8] contain address bits [15:8] for boot device accesses. The EBDA[15:8] signals are driven to a constant ...
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TX_EN transitions synchronous to TX_CLK rising edges. Note: The TX_EN pin is multiplexed with the TXEN pin. When RST is active, TX_EN is an input for NAND tree testing. If the MII port is not selected, ...
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If the MII port is not selected, the RX_DV pin can be left floating. RX_ER Receive Error RX_ER is an input that indicates that the MII trans- ceiver device has detected a coding error in the receive frame currently being ...
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RXCLK Receive Clock RXCLK is an input. The rising edges of the RXCLK sig- nal are used to sample the data on the RXDAT input whenever the RXEN input is HIGH. Note: The RXCLK pin is multiplexed with the RX_CLK ...
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SFD (Start of Frame Delimiter received frame. Data on the RXD[3:0] will be the start of the destination address field. SFBD will subsequently toggle every nib- ble time (1.25 MHz frequency when operating at 10 Mbps and ...
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When RST is active, MIIRXFRTGE is an input for NAND tree testing. IEEE 1149.1 (1990) Test Access Port Interface TCK Test Clock TCK is the clock input for the boundary scan test mode operation. It can operate at a frequency ...
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BASIC FUNCTIONS System Bus Interface The Am79C971 controller is designed to operate as a bus master during normal operations. Some slave I/O accesses to the Am79C971 controller are required in nor mal operations as well. Initialization of the Am79C971 controller ...
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DETAILED FUNCTIONS Slave Bus Interface Unit The slave bus interface unit (BIU) controls all accesses to the PCI configuration space, the Control and Status Registers (CSR), the Bus Configuration Registers (BCR), the Address PROM (APROM) locations, and the Expansion ROM. ...
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CLK FRAME ADDR AD 1010 C/BE BE PAR PAR IRDY TRDY DEVSEL STOP IDSEL DEVSEL is sampled Figure 1. Slave Configuration Read The Am79C971 controller will not assert DEVSEL if it detects an address match, but ...
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CLK 1 FRAME AD ADDR 0010 C/BE PAR IRDY TRDY DEVSEL STOP Figure 3. CLK 1 FRAME ADDR AD 0011 C/BE PAR IRDY TRDY DEVSEL STOP Figure 4. Slave Write Using Memory Command ...
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Expansion ROM Transfers The host must initialize the Expansion ROM Base Ad- dress register at offset 30H in the PCI configuration space with a valid address before enabling the access to the device. The Am79C971 controller will not react to ...
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During the boot procedure, the system will try to find an Expansion ROM. A PCI system assumes that an Ex- pansion ROM is present when it reads the ROM signa- ture 55H (byte 0) and AAH (byte 1). A design ...
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If the host is not yet ready when the Am79C971 control- ler asserts TRDY, the device will wait for the host to as- sert IRDY. When the host asserts IRDY and FRAME is still asserted, the Am79C971controller will finish the ...
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CLK 1 FRAME AD C/BE PAR PERR IRDY TRDY DEVSEL Figure 10. Slave Cycle Data Parity Error Response Master Bus Interface Unit The master Bus Interface Unit (BIU) controls the acqui- sition of the PCI bus and all accesses to ...
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Figure 11 shows the Am79C971controller bus acquisi- tion. REQ is asserted and the arbiter returns GNT while an othe tran sfer dat Am79C971 controller waits ...
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CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT3 DEVSEL is sampled CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0) 38 ...
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Basic Non-Burst Write Transfer By default, the Am79C971 controller uses non-burst cy cles bus ma ster wr ite operations. All Am79C971 controller non-burst write accesses are of the PCI command type Memory Write (type 7). The ...
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Figure 15 shows a typical burst write access. The Am79C971 controller arbitrates for the bus, is granted access, and writes four 32-bit words (DWords) to the system memory and then releases the bus. In this ex- ample, the memory system ...
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CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL STOP REQ GNT DEVSEL is sampled Figure 16. Disconnect With Data Transfer Disconnect Without Data Transfer Figure 17 shows a target disconnect sequence during which no data is transferred. STOP is ...
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CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL STOP REQ GNT DEVSEL is sampled Figure 17. Disconnect Without Data Transfer RTABORT (PCI Status register, bit 12) will be set to indicate that the Am79C971 controller has received a target ...
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CLK FRAME ADDR DATA AD 0000 C/BE 0111 PAR PAR IRDY TRDY DEVSEL STOP REQ GNT DEVSEL is sampled Figure 18. Target Abort When the preemption occurs after the counter has counted down to 0, ...
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FRAME C/BE IRDY TRDY DEVSEL REQ GNT Figure 19. Preemption During Non-Burst Transaction CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT Figure 20. Preemption During Burst Transaction 44 CLK ADDR DATA 0111 ...
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CLK FRAME AD ADDR C/BE 0111 PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 21. Master Abort CLK FRAME AD ADDR 0111 C/BE BE PAR PAR PERR IRDY TRDY ...
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Whenever the Am79C971 controller is the current bus master and a data parity error occurs, SINT (CSR5, bit 11) will be set to 1. When SINT is set, INTA is asserted if the enable bit SINTE (CSR5, bit 10) is ...
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If 512 bits or more have been transmitted, the message will have the current FCS inverted and appended at the next byte boundary to guarantee an FCS error is de- tected at the receiving station. APERREN does not affect the ...
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FRAME C/BE IRDY TRDY DEVSEL REQ Figure 24. Initialization Block Read In Burst Mode CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 25. Descriptor Ring Read In Non-Burst Mode 48 CLK 1 2 ...
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If buffer chaining is used, accesses to the descriptors of all intermediate buffers consist of only one data transfer to return ownership of the buffer to the system. When SWSTYLE (BCR20, bits 7-0) is cleared to 0 (i.e., the descriptor ...
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Table 5. Descriptor Write Sequence SWSTYLE BWRITE BCR20[7:0] BCR18[5] AD Bus Sequence Address = XXXX XX04h Data = MD2[15:0], MD1[15: Idle Address = XXXX XX00h Data = MD1[31:24] Address = XXXX XX08h Data = MD2[31: Idle ...
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CLK FRAME AD MD2 DATA 0111 0000 C/BE PAR PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 27. Descriptor Ring Write In Non-Burst Mode CLK FRAME MD2 AD ...
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Burst FIFO DMA Transfers Bursting is only performed by the Am79C971 controller if the BREADE and/or BWRITE bits of BCR18 are set. These bits individually enable/disable the ability of the Am79C971 controller to perform burst accesses during master read operations ...
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CLK FRAME ADD DATA DATA AD 0111 0000 C/BE PAR PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 30. FIFO Burst Write At End Of Unaligned Buffer The exact number of total transfer ...
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Note that this form of restart will not perform the same in the Am79C971 controller as in the C-LANCE device. In particular, upon restart, the Am79C971 controller re- loads the transmit and receive descriptor pointers with their respective base addresses. ...
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Note that even though the Am79C971 controller treats the descriptor entries as 16-bit structures, it will always perform 32-bit bus transfers to access the descriptor entries. The value of CSR2, bits 15-8, ...
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CSR2 IADR[31:16] Initialization Block MOD PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLE RES RDRA[23:16] TDRA[15:0] TLE RES TDRA[23:16] Note that the value of CSR2, bits 15-8, is used as the upper 8-bits for all memory addresses during bus ...
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CSR2 IADR[31:16] Initialization Block TLE RES RLE RES PADR[31:0] RES LADRF[31:0] LADRF[63:32] RDRA[31:0] TDRA[31:0] If RXON is cleared to 0, the Am79C971 controller will never poll RDTE locations. In order to avoid missing frames, the system should have at least ...
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If the OWN bit of the TDTE is set, but the Start of Packet (STP) bit is not set, the Am79C971 controller will immediately request the bus in order to clear the OWN bit of this descriptor. (This condition would ...
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If a poll operation has revealed that the current and the next RDTE belong to the Am79C971 controller, then additional poll accesses are not necessary. Future poll operations will not include RDTE accesses as long as the Am79C971 controller retains ...
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The default value of STVAL is FFFFh which yields the approximate maximum 838 ms timer duration. A write to STVAL restarts the timer with the new contents of STVAL. Media Access Control The Media Access ...
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MAC engine will automatically delete the frame from the receive FIFO, without host intervention. The Am79C971 controller has the ability to accept runt packets for diagnostic purposes and proprietary net- works. Destination Address Handling The first 6 bytes of ...
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Medium Allocation The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990) requires that the CSMA/CD MAC monitor the medium for traffic by watching for carrier activity. When carrier is detected, the media is considered busy, and the MAC should defer to the ...
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See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1): “At the conclusion of the output function, the DTE opens a time window during which it expects to see the signal_quality_error signal asserted on the Control In circuit. The time window begins when ...
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The disable FCS generation/transmission feature can be programmed as a static feature or dynamically on a frame-by-frame basis. Transmit FIFO Watermark (XMTFW) in CSR80 sets the point at which the BMU requests more data from the transmit buffers for the ...
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The default value of DXMTFCS is 0 after H_RESET. ADD_FCS (TMD1, bit 29) allows the automatic gener- ation and transmission of FCS on a frame-by-frame basis. DXMTFCS should be set this mode. To generate FCS for ...
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Receive Operation The receive operation and features of the Am79C971 controller are controlled by programmable options. The Am79C971 controller offers a large receive FIFO to provide frame buffering for increased system latency, automatic flushing of collision fragments (runt packets), automatic ...
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If DRCVBC (CSR15, bit 14) is cleared to 0, only BAM, but not LAFM will be set when a Broadcast frame is re- ceived, even if the Logical Address Filter is pro- grammed in such a way that a Broadcast ...
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Since any valid Ethernet Type field value will always be greater than a normal IEEE 802.3 Length field ( 46), the Am79C971 controller will not attempt to strip valid Ethernet frames. Note that for some network protocols, the value passed ...
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T-MAU Loopback Modes When T-MAU is the active network port there are four modes of loopback operation: internal loopback with and without MENDEC and two external loopback modes. When INTL and MENDECL are set to 1, internal loop- back without ...
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Manchester Encoder/Decoder The integrated Manchester Encoder/Decoder (MEN- DEC) provides the PLS (Physical Layer Signaling) functions required for a fully compliant ISO 8802-3 (IEEE/ANSI 802.3) station. The MENDEC provides the encoding function for data to be transmitted on the net- work ...
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Receiver Path The principal functions of the receiver are to signal the Am79C971 controller that there is information on the receive pair and to separate the incoming Manchester encoded data stream into clock and NRZ data. The receiver section consists ...
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The time delay from the last rising edge of the message to IRXEN deassert allows the last bit to be strobed by IRXCLK and transferred to the controller section, but prevents any extra bit(s) at the end of message. Data ...
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ANSI 802.3) Standard. The transmit function for data output meets the propagation delays and jitter speci- fied by the standard. Twisted Pair Receive Function The receiver complies with the receiver specifications of the ISO 8802-3 (IEEE/ANSI 802.3) 10BASE-T Stan- dard, ...
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This negative excur- sion may be followed by a positive excursion. This def- inition is consistent with the expected received signal at a reverse wired receiver, when a link beat pulse, ...
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General Purpose Serial Interface The General Purpose Serial Interface (GPSI) provides a direct interface to the MAC section of the Am79C971 controller. All signals are digital and data is non-en- coded. The GPSI allows use of an external Manchester encoder/decoder ...
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XMTFW bits (CSR80, bits 9-8) al- ways govern when transmit DMA is requested. Successful reception of the first 64 bytes of every receive frame is not a requirement for Receive DMA to begin as described in the Receive ...
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RXD(3:0), from the exter nal PHY to the Am79C971 controller and is synchronous to the rising edge of RX_CLK. The receive process starts when RX_DV is asserted. RX_DV will remain asserted until the end of the receive frame. The ...
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The MII Management Interface has a built-in detection system to allow the Am79C971 controller to determine if an external PHY is attached. The MDIO I/O pin has a resistor network between the Am79C971 controller and the external PHY that will ...
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Registers, for the bit descriptions of the MII Status Register. The contents of the latest read from the external PHY will be stored in a shadow register in the Auto-Poll block. The first read of the MII Status Reg- ...
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Am79C971 control- ler will always defer to the software driver. When The ASEL is set to 0, the software driver should then con- figure the ports with PORTSEL (CSR15, bits 7-8). The GPSI does ...
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PHY is attached to the MII Management Inter- face, then the DANAS (BCR32, bit 7) bit must be set to 1 and then all configuration control should revert to software. The Am79C971 controller will read the MII Status register ...
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The SFBD signal will initially be LOW. The assertion of SFBD is a signal to the external address detection logic that the SFD has been detected and that subsequent SRDCLK cycles will deliver packet data to the external logic. Therefore, ...
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SFBD signal will go HIGH at each new byte boundary within the packet, subsequent to the SFD. This eliminates the need for ex- ternally supplying byte framing logic. The EAR pin function is the same and ...
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SRDCLK SRD SFBD MIIRXFRTGE MIIRXFRTGD Figure 41. Internal PHY Receive Frame Tagging Expansion Bus Interface The Am79C971 controller contains an Expansion Bus Interface that supports two different boot devices, EPROM and Flash, as well as SRAM used as an exten- ...
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EBUA_EBA[7:0] Am79C971 Figure 42. SRAM and Flash Configuration for the Expansion Bus The time that the Am79C971 controller waits for data to be valid is programmable. ROMTMG (BCR18, bits 15- 12) defines the time from when the Am79C971 control- ler ...
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Am79C971 Figure 43. EPROM Only Configuration for the Expansion Bus (64K EPROM) After the Expansion ROM is enabled, the Am79C971 controller will claim all memory read accesses with an address between ROMBASE and ROMBASE + (ROMBASE, PCI ...
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EBD[7:0] Am79C971 EBWE ERAMCS EBUA_EBA[7:0] EROMCS EBDA[15:8] AS_EBOE Figure 44. EPROM Only Configuration for the Expansion Bus (>64K EPROM) '374 D-FF A[19:16] A[15:8] A[7:0] EPROM DQ[7: Am79C971 20550D-47 87 ...
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EBCLK EBUA_EBA[7:0] EBDA[15:8], EBD[7:0] ERAMCS EBWE AS_EBOE t_AS_L Figure 45. Expansion ROM Bus Read Sequence CLK EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS AS_EBOE Figure 46. Flash Read from Expansion Bus Data Port 88 Upper Lower Address Address tv_A_D DATA t_CS_L t_WE_L t_AS_H ...
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The EROMCS is driven low for the value ROMTMG + 1. Figure 46 assumes that ROMTMG is set to nine. EBD[7:0] is sampled with the next rising edge of CLK ten clock cycles after EBUA_EBA[7:0] was driven with a new ...
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Bus Write Command Cycles First Bus Sequence Req’d Write Cycle Addr Data Byte Program 4 5555h AAh Chip Erase 6 5555h AAh Sector Erase 6 5555h AAh SRAM Configuration The Am79C971 controller supports SRAM as a FIFO extension as well ...
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EBD[7:0] EBWE ERAMCS EBUA_EBA[7:0] '374 D-FF AS_EBOE EBDA[15:8] Am79C971 Figure 48. SRAM Only Configuration for the Expansion Bus Expansion Bus Interface Bus Rcv FIFO PCI Bus Interface Unit Bus Xmt FIFO Buffer FIFO Management Control Unit Figure 49. Block Diagram ...
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No SRAM Configuration If the SRAM_SIZE (BCR25, bits 7-0) value the SRAM size register, the Am79C971 controller will as- sume that there is no SRAM present and will reconfig- ure the four internal FIFOs into two FIFOs, ...
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PCI Bus Interface Unit Buff er Management Unit Figure 51. Block Diagram Low Latency Receive Configuration SRAM Accesses The SRAM access during normal operations is a single cycle address load to fill the upper bits into the ‘374 fol- lowed ...
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EBCLK EBD[15:0] EBUA_EBA[7:0] AS_EBOE EBWE ERAMCS Note: EBD[15:0] = EBDA[15:8]+EBD[7:0] Figure 53. SRAM Interface Bandwidth Requirements When the EBCLK pin is used to drive the Expansion Bus cycles and external SRAMs are present, the CLK_FAC (BCR27, bits 2-0) selects the ...
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If the user wishes to modify any of the configuration bits that are contained in the EEPROM, then the seven command, data and status bits of BCR19 can be used to write to the EEPROM. After writing to the EEPROM, ...
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Word Byte Address Addr. Most Significant Byte 2nd byte of the ISO 8802-3 (IEEE/ANSI 00h* 01h 802.3) station physical address for this node 01h 03h 4th byte of the node address 02h 05h 6th byte of the node address 03h ...
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There are two checksum locations within the EE- PROM. The first checksum will be used by AMD driver software to verify that the ISO 8802-3 (IEEE/ANSI 802.3) station address has not been corrupted. The value of bytes 0Ch and 0Dh ...
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SLEEP pin is driven LOW. All other sections of the device are shut down except the LED0 pin, the only LED pin that con- tinues to function, just as in normal operation. The ...
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Magic Packet mode. Once either of these events has occurred indicating that the system has de- tected the assertion of INTA or an LED pin and is now awake, the controller will continue polling the receive and transmit descriptor ...
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Other Data Registers Other data registers are the following: 1. Bypass Register (1 bit) 2. Device ID register (32 bits) (Table 17). Table 17. Device ID Register Bits 31-28 Version Bits 27-12 Part Number (0010 0110 0010 0011) Manufacturer ID. ...
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RST CLK GNT REQ AD[31:0] FFFFFFFF C/BE[3:0] IDSEL FRAME IRDY TRDY DEVSEL STOP PERR SERR PAR ... INTA NAND Tree Input NAND Tree No. Pin No. Name 1 143 RST 25 2 145 CLK 26 3 147 GNT 27 4 ...
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Reset There are three different types of RESET operations that may be performed on the Am79C971 device, H_RESET, S_RESET, and STOP. The following is a de- scription of each type of RESET operation. H_RESET Hardware Reset (H_RESET Am79C971 ...
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Table 19 Device ID Status Base-Class Sub-Class Reserved Header Type Memory Mapped I/O Base Address Subsystem ID Expansion ROM Base Address MAX_LAT MIN_GNT I/O Resources The Am79C971 controller requires 32 bytes of address space for access to ...
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IEEE station address. It can be overwritten by the host computer and its content has no effect on the op- eration of the controller. The software must copy the station address from the Address PROM space to the initialization ...
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The DWIO mode can be configured from the EEPROM or programmed by the software. Note: Even though the I/O resource mapping changes when the I/O mode setting changes, the RDP location offset is the same for both modes. Once the ...
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Table 23. Legal I/O Accesses in Word I/O Mode (DWIO = 0) AD[4:0] BE[3:0] Type 0XX00 1110 RD 0XX01 1101 RD 0XX10 1011 RD 0XX11 0111 RD 0XX00 1100 RD 0XX10 0011 RD 10000 1100 RD 10010 0011 RD 10100 ...
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PCI Configuration Registers These registers are intended to be initialized by the system initialization procedure (e.g., BIOS device ini- tialization routine) to program the operation of the Am79C971 controller PCI bus interface. The following is a list of the registers ...
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The following is a list of the registers that would typically need to be periodically read and perhaps written during the normal running operation of the Am79C971 control- ler within a system. Each of these registers contains control bits, or ...
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SERR pin and the SERR bit in the PCI Status register. PERREN is H_RESET and is not effected by S_RESET or by setting the STOP bit. 5 VGASNOOPVGA Palette Snoop. Read as ze- ro; write operations have ...
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In master mode, during the data phase of all memory read com- mands. In master mode, during the data phase of the memory write com- mand, the Am79C971 controller sets the PERR bit if the target re- ports a ...
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RES Reserved locations. Read as ze- ro; write operations have no ef- fect. PCI Revision ID Register Offset 08h The PCI Revision ID register is an 8-bit register that specifies the Am79C971 controller revision number. The value of this ...
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I/O space. IOBASE must be written with a valid address be- fore the Am79C971 controller slave I/O mode is turned on by setting the IOEN bit (PCI Com- mand register, bit 0). When the Am79C971 controller is enabled ...
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MEMSPACE Memory space indicator. Read as zero; write operations have no effect. Indicates that this base ad- dress register describes a memo- ry base address. PCI Subsystem Vendor ID ...
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ROMEN is read and written by the host. ROMEN is cleared by H_RESET and is not effected by S_RESET or by setting the STOP bit. PCI Interrupt Line Register Offset 3Ch The PCI Interrupt Line register is an 8-bit register ...
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Read/Write accessible always. RAP is cleared by H_RESET or S_RESET and is unaffected by setting the STOP bit. Control and Status Registers The CSR space is accessible by performing accesses to the RDP (Register ...
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IENA and MISSM. Read/Write accessible always. MISS is cleared by the host by writing a 1. Writing a 0 has no ef- fect. MISS H_RESET, S_RESET set- ting the STOP bit. 11 ...
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Read accessible always. INTR is read only. INTR is cleared by clearing all of the active individual interrupt bits that have not been masked out. 6 IENA Interrupt Enable allows INTA to be active if the Interrupt Flag is set. ...
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H_RESET, S_RESET setting the STOP bit. CSR1: Initialization Block Address 0 Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 IADR[15:0] Lower 16 bits of the address of the Initialization Block. ...
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RES Reserved location. Read and written as zero. 12 MISSM Missed Frame Mask. If MISSM is set, the MISS bit will be masked and unable to set the INTR bit. Read/Write accessible always. MISSM is cleared by H_RESET or ...
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STP = 1, then some descriptors/ buffers may be skipped in the ring. While performing the search for the next STP bit that is set to 1, the Am79C971 controller will advance through the receive de- scriptor ring regardless of ...
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BSWP bit. Descriptor transfers are not affected by the setting of the BSWP bit. RDP, RAP, BDP and PCI configuration space ac- cesses are not affected by the setting of the BSWP bit. Address PROM transfers are not affected by ...
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ASTRP_RCV Auto Strip Receive. When set, ASTRP_RCV enables the auto- matic pad stripping feature. The pad and FCS fields will be stripped from receive frames and not placed in the FIFO. Read/Write accessible always. ASTRP_RCV H_RESET or S_RESET and ...
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JAB Jabber Error is set by the Am79C971 controller when the T-MAU exceeds the allowed transmission limit. Jabber can only be asserted in 10BASE-T mode. When JAB is set, INTA is assert IENA is 1 and the ...
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SLPINT Sleep Interrupt is set by the Am79C971 controller when it comes out of sleep mode. When SLPINT is set, INTA is as- serted if the enable bit SLPINTE is 1. Note that the assertion of an interrupt due ...
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MPEN Magic Packet Enable. MPEN al- lows activation of the Magic Packet mode by the host. The Am79C971 controller will enter the Magic Packet mode when both MPEN and MPMODE are set to 1. Read/Write accessible always. MPEN is ...
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CSR7: Extended Control and Interrupt 2 Certain bits in CSR7 indicate the cause of an interrupt. The register is designed so that these indicator bits are cleared by writing ones to those bit locations. This means that the software can ...
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Read/Write accessible always. RDMD is set by writing a 1. Writ- ing a 0 has no effect. RDMD will be cleared by the Buffer Manage- ment Unit when it fetches a re- ceive Descriptor. cleared by H_RESET. RDMD is unaffected ...
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When MAPINT is set to 1, INTA is asserted if the enable bit MAP- INTE is set to 1. Read/Write accessible always. MAPINT is cleared by the host by writing a 1. Writing a 0 has no ef- fect. MAPINT ...
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MIIPDTINT MII PHY Detect Transition Inter- rupt. The MII PHY Detect Transi- tion Interrupt is set by the Am79C971 controller whenever the MIIPD bit (BCR32, bit 14) transitions from vice ver- sa. Read/Write accessible always. ...
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PADR[15:0] Physical Address PADR[15:0]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSR0 has been set or a direct register write has been performed on this register. Read/Write accessible ...
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Like- wise, when polarity reversal algorithm is en- abled. This bit only has meaning when the 10BASE-T network interface is selected. Read/Write accessible only when either the STOP or the SPND bit ...
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ASEL PORTSEL [1:0] (BCR2[1 DRTY Disable Retry. When DRTY is set to 1, the Am79C971 controller will attempt only one transmission. In this mode, the ...
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Read/Write accessible only when either the STOP or the SPND bit is set. LOOP is cleared by H_RESET or S_RESET and is unaffected by STOP. 1 DTX Disable Transmit Am79C971 controller not access- ing the Transmit Descriptor Ring and, therefore, ...
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CXBAU Contains the upper 16 bits of the current transmit buffer address from which the Am79C971 con- troller is transmitting. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, ...
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CRDAL Contains the lower 16 bits of the current receive descriptor ad- dress pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR29: Current Receive ...
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CXDAU Contains the upper 16 bits of the current transmit descriptor ad- dress pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR36: Next Next ...
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CSR42: Current Transmit Byte Count Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-12 RES Reserved locations. Read and written as zeros. 11-0 CXBC Current Transmit Byte Count. This field is a copy of ...
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The default value of this register is 0000b. This corresponds to a polling interval of 65,536 clock periods (1.966 CLK = 33 MHz). The TXPOL- LINT value of 0000b is created during the microcode initialization routine and, therefore, might not ...
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If the user does not use the stan- dard initialization (standard implies use of an initial- ization block in memory and set- ting the INIT bit of CSR0), but instead, chooses to write directly to each of the registers that ...
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SSIZE32 bit. Note that the setting of the SSIZE32 bit has no effect on the defined width for I/O resources. I/O resource width is determined by the state ...
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CSR62: Previous Transmit Byte Count Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-12 RES Reserved locations. 11-0 PXBC Previous Transmit Byte Count. This field is a copy of the BCNT field of TMD1 ...
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CSR72: Receive Ring Counter Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 RCVRC Receive Ring Counter location. Contains a two’s complement bi- nary number used to number the current receive descriptor. This counter ...
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DMA is requested. Note however that, if the network interface is op- erating in half-duplex mode, in or- der for receive DMA to be performed for a new frame, ...
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When an external SRAM is used, SRAM_SIZE > 0, there is a re- striction that the number of bytes written is a combination of bytes written into the Bus Transmit FIFO and the MAC Transmit FIFO. The Am79C971 controller supports ...
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TXDAPL Contains the lower 16 bits of the transmit descriptor address cor- responding to the last buffer of the previous transmit frame. If the previous transmit frame did not use buffer chaining, then TXDA- PL contains the lower 16 ...
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ID as that stored in the Device ID register in the PCI con- figuration space. Read accessible only when either the STOP or the SPND bit is set. VER is read only. PARTID is read only. Write operations ...
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Read/Write accessible only when either the STOP or the SPND bit is set. This register is set to 0600h by S_RESET and is unaffected by STOP. CSR112: Missed Frame Count Bit Name Description 31-16 RES Reserved locations. Written as zeros ...
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RES Reserved locations. Written as zeros and read as undefined. 15-8 IPG Inter Packet Gap. Changing IPG allows the user to program the Am79C971 controller for aggres- siveness on a network. By chang- ing the default value of 96 ...
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Note that several registers have no default value. BCR0, BCR1, BCR3, BCR8, BCR10-17, and BCR21 are reserved and have undefined values. BCR2 and BCR34 are not observable without first being pro- grammed through the EEPROM read operation or a user ...
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BCR1: Master Mode Write Active Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 MSWRA Reserved H_RESET, the value in this regis- ter will be 0005h. The setting of this register has no effect ...
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INTLEVEL should not be set to 1 when the Am79C971 controller is used in a PCI bus application. Read/Write accessible always. INTLEVEL is cleared H_RESET and is unaffected by ...
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ASEL PORTSEL[1:0] (BCR2[1 BCR4: LED0 Status BCR4 controls the function(s) that the LED0 pin dis- plays. Multiple functions can be simultaneously en- abled on this LED ...
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Mbps Enable. When this bit is set value passed to the LEDOUT bit in this register when the Am79C971 controller is operating at 100 Mbps mode. The indication is valid with ...
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PSE Pulse Stretcher Enable. When this bit is set, the LED illumination time is extended for each new oc- currence of the enabled function for this LED output. A value of 0 disables the pulse stretcher. Read/Write accessible always. ...
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BCR5: LED1 Status BCR5 controls the function(s) that the LED1 pin dis- plays. Multiple functions can be simultaneously en- abled on this LED pin. The LED display will indicate the logical OR of the enabled functions. BCR5 defaults to Receive ...
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DXCVRCTL DXCVR Control. When the AUI interface is the active network port, DXCVRCTL controls the as- sertion of the LED1 output. The polarity of the asserted state is controlled by the LEDPOL bit (BCR4, bit 14). The LED1 pin ...
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RCVME Receive Match Status Enable. When this bit is set, a value passed to the LEDOUT bit in this register when there is receive ac- tivity on the network that has passed the address match func- ...
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LEDPOL LED Polarity. When this bit has the value 0, then the LED pin will be driven to a LOW level whenev- er the OR of the enabled signals is true, and the LED pin will be disabled and ...
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MPSE Magic Packet Status Enable. When this bit is set value passed to the LEDOUT bit in this register when Magic Packet frame mode is enabled and a Magic Packet frame is detected ...
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Read/Write accessible always. RXPOLE is set H_RESET and is not affected by S_RESET or setting the STOP bit. 2 RCVE Receive Status Enable. When this bit is set, a value passed to the LEDOUT ...
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LEDDIS LED Disable. This bit is used to disable the LED output. When LEDDIS has the value 1, then the LED output will always be dis- abled. When LEDDIS has the val then the LED output value ...
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FDEN and AUIFD bits in BCR9 are set to 1). Read/Write accessible always. FDLSE is cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. 7 PSE Pulse Stretcher Enable. When this bit is set, the ...
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Read/Write accessible always. COLE is cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. BCR9: Full-Duplex Control Note: Bits 15-0 in this register are programmable through the EEPROM. Bit Name Description 31-16 RES Reserved locations. ...
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RES Reserved locations. Written as zeros, read as undefined. AUIFD (bit FDEN (bit Effect on the AUI 1) 0) Port X 0 Half-Duplex 0 1 Half-Duplex 1 1 Full-Duplex BCR17: I/O Base Address Upper Bit Name Description 31-16 RES ...
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For an adapter card application, the value used for clock period should guarantee cor- rect interface timing at the maxi- mum clock frequency of 33 MHz. Read accessible always; write accessible only when the STOP bit ...
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EXTREQ should not be set to 1 when the Am79C971 controller is used in a PCI bus application. Read accessible always, write accessible only when either the STOP or the SPND bit is set. EX- TREQ is cleared by H_RESET ...
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BCR19: EEPROM Control and Status Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15 PVALID EEPROM Valid status bit. Read accessible only. PVALID is read only; write operations have no ef- fect. A value ...
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DEVSEL and STOP while TRDY is not asserted, sig- naling to the initiator to discon- nect and retry the access at a later time PREAD command is given to the Am79C971 controller but no EEPROM is ...
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PREAD = 0 and ECS is set then the EECS pin will be forced to a HIGH level at the ris- ing edge of the next clock follow- ing bit programming. If EEN = 1 and ...
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PREAD or Auto RST Pin Read in Progress Low X High 1 High 0 High 0 BCR20: Software Style This register is an alias of the location CSR58. Accesses to and from this register are equivalent to accesses to CSR58. ...
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The value of the SSIZE32 bit has no effect on the drive of the upper 8 address bits. The upper 8 ad- dress pins are always driven, re- gardless of the state of the SSIZE32 bit. Note that the setting ...
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EEPROM. MAX_LAT is not affected by S_RESET or STOP. 7-0 MIN_GNT Minimum Grant. Specifies the minimum length of a burst period the Am79C971 controller needs to keep up with the network activ- ...
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SRAM_SIZE SRAM Size. Specifies the upper 8 bits of the 16-bit total size of the SRAM buffer. SRAM_SIZE accounts for a 512- byte page. The starting address for the lower 8 bits is assumed to be 00h and the ...
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Note: Use of this bit will cause data corruption and erroneous operation. Read/Write accessible always. PTR_TST is H_RESET and is unaffected by S_RESET and the STOP bit. 14 LOLATRX Low Latency Receive. When the LOLATRX bit is set to 1, ...
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CAUTION: Care should be ex- ercised when choosing the PCI clock pin because of the nature of the PCI clock signal. The PCI specification states that the PCI clock can be stopped. If that can occur while it is being ...
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EBDATA (BCR30). When EBADDRL reaches FFFFh and LAAINC is set to 1, the Expansion Port Lower Address (EPADDRL) will roll over to 0000h. When the LAAINC bit is set to 0, the Expan- sion Port Lower Address will ...
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The STVAL value is interpreted as an unsigned number with a resolution of 12.8 stance, a value of 122 ms would be programmed with a value of 9531 (253Bh). A value un- defined and will result in ...
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Read/Write accessible always. APEP is set H_RESET and is unaffected by S_RESET and the STOP bit. 10-8 APDW MII Auto-Poll Dwell Time. APDW determines the dwell time be- tween MII Management Frames accesses when turned on. See Table 41. Table ...
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Am79C971 con- troller to work seamlessly with the Micro Linear 6692 PHY. See the section on Working with Micro Linear 6692 for details. Read/Write accessible always. MII L is set H_RESET and is ...
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BCR34: MII Management Data Register Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 MIIMD MII Management Data. MIIMD is the data port for operations on the MII management interface (MDIO and MDC). The ...
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Table 42. Initialization Block (SSIZE32 = 0) Address Bits 15-13 IADR+00h IADR+02h IADR+04h IADR+06h IADR+08h IADR+0Ah IADR+0Ch IADR+0Eh IADR+10h IADR+12h RLEN IADR+14h IADR+16h TLEN Table 43. Initialization Block (SSIZE32 = 1) Bits Bits Address 31-28 27-24 IADR+00h TLEN RES ...
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Table 45. R/TLEN Decoding (SSIZE32 = 1) R/TLEN Number of DREs 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 11XX 1X1X LADRF The Logical Address Filter (LADRF 64-bit mask that is used to accept incoming Logical ...
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Mode The mode register field of the initialization block is cop- ied into CSR15 and interpreted according to the de- scription of CSR15. Receive Descriptors When SWSTYLE (BCR20, bits 7-0) is set to 0, then the software structures are defined ...
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Once the Am79C971 controller or host has relinquished ownership of a buffer, it must not change any field in the descriptor entry. 30 ERR ERR is the OR of FRAM, OFLO, CRC, BUFF, or BPE. ERR is set by the ...
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PAM is valid only when ENP is set. PAM is set by the Am79C971 controller and cleared by the host. This bit does ...
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RMD3 Bit Name Description 31-0 US User Space. Reserved for user defined space. Transmit Descriptors When SWSTYLE (BCR20, bits 7-0) is set to 0, the soft- ware structures are defined bits wide, and transmit descriptors look like ...
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TMD1 Bit Name Description 31 OWN This bit indicates whether the de- scriptor entry is owned by the host (OWN = the Am79C971 controller (OWN = 1). The host sets the OWN bit after filling the buffer ...
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ENP End of Packet indicates that this is the last buffer to be used by the Am79C971 controller for this frame used for data chaining buffers. If both STP and ENP are set, the frame fits into ...
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Excessive De- ferral is defined in the ISO 8802-3 (IEEE/ANSI 802.3) standard. Ex- cessive Deferral will also set the interrupt bit EXDINT (CSR5, bit 7). 28 LCOL Late Collision indicates that a col- lision has occurred after ...
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REGISTER SUMMARY PCI Configuration Registers Offset Name 00h PCI Vendor ID 02h PCI Device ID 04h PCI Command 06h PCI Status 08h PCI Revision ID 09h PCI Programming IF 0Ah PCI Sub-Class 0Bh PCI Base-Class 0Ch Reserved 0Dh PCI Latency ...
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Control and Status Registers RAP Addr Symbol Default Value 00 CSR0 uuuu 0004 01 CSR1 uuuu uuuu 02 CSR2 uuuu uuuu 03 CSR3 uuuu 0000 04 CSR4 uuuu 0115 05 CSR5 uuuu 0000 06 CSR6 uuuu uuuu 07 CSR7 0uuu ...
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CONTROL AND STATUS REGISTERS (CONTINUED) RAP Default Value Addr Symbol After H_RESET Comments 34 CSR34 uuuu uuuu 35 CSR35 uuuu uuuu 36 CSR36 uuuu uuuu 37 CSR37 uuuu uuuu 38 CSR38 uuuu uuuu 39 CSR39 uuuu uuuu 40 CSR40 uuuu ...
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Control and Status Registers (Continued) RAP Default Value Addr Symbol After H_RESET Comments 71 CSR71 uuuu uuuu 72 CSR72 uuuu uuuu 73 CSR73 uuuu uuuu 74 CSR74 uuuu uuuu 75 CSR75 uuuu uuuu 76 CSR76 uuuu uuuu 77 CSR77 uuuu ...
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CONTROL AND STATUS REGISTERS (CONCLUDED) RAP Default Value Addr Symbol After H_RESET Comments 108 CSR108 uuuu uuuu 109 CSR109 uuuu uuuu 110 CSR110 uuuu uuuu 111 CSR111 uuuu uuuu 112 CSR112 uuuu uuuu 113 CSR113 uuuu uuuu 114 CSR114 uuuu ...
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Bus Configuration Registers Writes to those registers marked as “Reserved” will have no effect. Reads from these locations will produce unde- fined values. RAP Mnemonic 0 MSRDA 1 MSWRA Reserved 4 LED0 5 LED1 6 LED2 7 ...
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REGISTER PROGRAMMING SUMMARY Am79C971 Programmable Registers Am79C971 Control and Status Registers Register CSR0 Status and control bits: (DEFAULT = 0004) 8000 ERR 4000 BABL 2000 CERR 1000 MISS CSR1 Lower IADR (Maps to CSR 16) CSR2 Upper IADR (Maps to ...
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AM79C971 CONTROL AND STATUS REGISTERS (CONTINUED) Register CSR58 Software Style (mapped to BCR20) bits [7:0] = SWSTYLE, Software Style Register. 0000 0002 8000 -- 4000 -- 2000 -- 1000 -- CSR76 RCVRL: RCV Descriptor Ring length CSR78 XMTRL: XMT Descriptor ...
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Am79C971 Bus Configuration Registers RAP Addr Register 0 MSRDA Programs width of DMA read signal (DEFAULT = 5) 1 MSWRA Programs width of DMA write signal (DEFAULT = Miscellaneous Configuration bits: (DEFAULT = 2) 8000 -- 4000 ...
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AM79C971 BUS CONFIGURATION REGISTERS (CONTINUED) 20 SWSTYLE Software Style (DEFAULT = 0000, maps to CSR 58) 21 INTCON Interrupt Control 8000 4000 2000 1000 22 PCILAT PCI Latency (DEFAULT = FF06) bits [15:8] = MAX_LAT bits [7:0] = MIN_GNT 25 ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature ........................ – +150 C Ambient Temperature .......................... - +70 C Supply voltage with respect SSB SSM SS_PLL ............................. –0.3 ...