TLE7237SL Infineon Technologies, TLE7237SL Datasheet - Page 26
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TLE7237SL
Manufacturer Part Number
TLE7237SL
Description
IC DRIVER SPI RELAY CTRL 24SSOP
Manufacturer
Infineon Technologies
Series
-r
Type
High Side/Low Side Driverr
Datasheet
1.TLE7237SL.pdf
(36 pages)
Specifications of TLE7237SL
Input Type
SPI
Number Of Outputs
8
On-state Resistance
900 mOhm, 1.6 Ohm
Current - Output / Channel
175mA, 380mA
Current - Peak Output
500mA, 1A
Voltage - Supply
9 V ~ 16 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
24-SSOP (0.154", 3.90mm Width)
Packages
PG-SSOP-24
Channels
8.0
Rds (on) (typ)
0.9 Ohm
Vdd
3.0 - 5.5 V
Vds(cl)
41.0 - 52.0 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TLE7237SL
Manufacturer:
INFINEON
Quantity:
100
Part Number:
TLE7237SL
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
9
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
Figure 8
The SPI protocol is described in
9.1
CS - Chip Select: The system micro controller selects the TLE7237SL by means of the CS pin. Whenever the pin
is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are
ignored and SO is forced into a high impedance state.
CS High to Low transition:
•
•
Figure 9
Data Sheet
The diagnosis information is transferred into the shift register.
SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. For details, please refer to
available to the first rising edge of SCLK.
SCLK
SO
CS
time
SI
Serial Peripheral Interface (SPI)
Serial Peripheral Interface
SPI Signal Description
Transmission Error Flag on SO Line
SI
CS
MSB
MSB
SI
SCLK
CS
TER
S
Section
SPI
6
6
OR
5
5
9.3. It is reset to the default values after reset.
SO
S
4
4
1
0
3
3
26
2
2
SPI Driver for Enhanced Relay Control
SO
1
1
LSB
LSB
Figure
Serial Peripheral Interface (SPI)
9. This information stays
Rev. 1.1, 2011-04-05
TER.emf
TLE7237SL
SPI.emf