NOII5SM1300A-QWC ON Semiconductor, NOII5SM1300A-QWC Datasheet - Page 13

• Manufacturer Part Number: NOII5SM1300A-QWC
• Manufacturer: ON Semiconductor

Specifications of NOII5SM1300A-QWC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Analog-to-Digital Converter
The IBIS5-1300 has a 10-bit flash analog digital converter
running nominally at 40 Msamples/s. The ADC is electrically
separated from the image sensor. Tie the input of the ADC
(ADC_IN; pin 69) externally to the output (PXL_OUT1; pin 28) of
the output amplifier.
Table 14. ADC Specifications
Setting ADC Reference Voltages
Figure 14. Internal and External ADC Connections
Input range
Quantization
Nominal data rate
DNL (linear conversion mode) Typ. < 0.5 LSB
INL (linear conversion mode)
Input capacitance
Power dissipation at 40 MHz
Conversion law
Note
6. The internal ADC range is typically 100 mV lower then the external applied ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal resistors
ADC_VHIGH ~ 2.7V
ADC_VLOW ~ 1.8V
in the ADC.
R
ADC
R
R
external
external
ADC_VHIGH
ADC_VLOW
internal
1–3 V
10 bits
40 Msamples/s
Typ. < 3 LSB
< 20 pF
Typ. 45 mA × 3.3 V = 150 mW
Linear / Gamma-corrected
[6]
Rev. 9 | www.onsemi.com | Page 13 of 34
Figure 13. ADC Timing
ADC Timing
At the rising edge of SYS_CLOCK, the next pixel is fed to the
input of the output amplifier. Due to internal delays of the
SYS_CLOCK signal, it takes approximately 20 ns before the
output amplifier outputs the analog value of the pixel, as shown
in
The ADC converts the pixel data on the rising edge of the
ADC_CLOCK, but it takes two clock cycles before this pixel data
is at the output of the ADC.
Due to these delays, it is advisable that a variable phase
difference is foreseen between the ADC_CLOCK and the
SYS_CLOCK to tune the optimal sample moment of the ADC.
The internal resistor R
This results in the following values for the external resistors:
Note that the recommended ADC resistor values yield in a
conversion of the full analog output swing at unity gain
(V
ADC_VLOW).
The values of the resistors depend on the value of R
assure proper working of the ADC, make certain the voltage
difference between ADC_VLOW and ADC_VHIGH is at least
1.0 V.
R
R
R
ADC_VHIGH
ADC
ADC_VLOW
DARK_ANALOG
Figure
13.
Resistor
<
ADC_VHIGH
ADC
has a value of approximately 585 .
Figure 13
shows this pipeline delay.
and
NOII5SM1300A
V
Value (O)
LIGHT_ANALOG
1200
360
585
ADC
. To
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