AFBR-79E4Z Avago Technologies US Inc., AFBR-79E4Z Datasheet - Page 9

• Manufacturer Part Number: AFBR-79E4Z
• Description: 56T4986
• Manufacturer: Avago Technologies US Inc.

Specifications of AFBR-79E4Z

• Applications: Gigabit Ethernet
• Data Rate Max: 10.3125Gbps
• Supply Voltage: 3.3V
• Wavelength Typ: 850nm
• Lead Free Status / Rohs Status: Compliant

Receiver Optical Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical
values are for Tc = 40°C, Vcc = 3.3 V
*
Note:
1. The receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical input signal having this power level on one
2. Vertical eye closure penalty and stressed eye jitter are test conditions for measuring stressed receiver sensitivity. They are not characteristics of the
TP0 : Host ASIC transmitter output at ASIC package contact on the Host board
TP1 : Host ASIC transmitter output across the Host Board at the input side of the Host QSFP+ electrical connector
TP1a : Host ASIC transmitter output across the Host board at the output side of the Host QSFP+ electrical connector
TP2 : QSFP+ transmitter optical output at the end of a 2m to 5m patch cord
TP3 : QSFP+ receiver optical input at the end of the fiber
TP4a : QSFP+ receiver electrical output at the input side of the Host QSFP+ electrical connector
TP4 : QSFP+ receiver electrical output at the output side of the Host QSFP+ electrical connector
TP5 : Host ASIC receiver input at ASIC package contact on the Host board
Figure 6. Test point definitions
9
Parameter
(From Table 86-8 of IEEE 802.3ba)
Center wavelength, each lane
Damage Threshold
Maximum Average power at receiver
input, each lane
Receiver Reflectance
Optical Modulation Amplitude
(OMA), each lane
Stressed receiver sensitivity in OMA,
each lane
Conditions of stressed receiver
sensitivity:
Peak power, each lane
LOS Assert
LOS De-Assert – OMA
LOS Hysteresis
See Figure 6 for Test Point definitions.
lane. The receiver does not have to operate correctly at this input power
receiver. The apparent discrepancy between VECP and TDP is because VECP is defined at eye center while TDP is defined with ±0.15 UI offsets of
the sampling instant
OMA of each aggressor lane
Vertical Eye Closure Penalty,
each lane
Stressed eye J2 Jitter,
each lane
Stressed eye J9 Jitter,
each lane
SerDes
ASIC/
TP 0
2
1
TP 1
TP 1a
QSFP + TX
Test Point*
TP3
TP3
TP3
TP3
TP3
TP3
TP3
TP3
TP3
TP3
TP3
TP3
TP3
TP3
TP3
TP 2
840
Min
-30
3.4
0.5
Fiber
0.30
0.47
850
-0.4
Typ
1.9
Max
860
-5.4
-7.5
2.4
-12
3
4
TP 3
QSFP + RX
Units
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
nm
dB
dB
dB
UI
UI
TP 4a
Notes/Conditions
Measured with conformance test
signal at TP3 for BER = 10e-12
TP 4
TP 5
SerDes
ASIC/